digital equipment corporation maynard, massachusetts VAX 10000 Pocket Service Guide Order Number EK1000APG.001 This manual is intended for Digital service engineers. It supplies easy­to­ access key information on VAX 10000 systems. First Printing, February 1993 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. The software, if any, described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license. No re­ sponsibility is assumed for the use or reliability of software or equipment that is not supplied by Digital Equipment Corporation or its affiliated companies. Copyright © 1993 by Digital Equipment Corporation. All Rights Reserved. Printed in U.S.A. The following are trademarks of Digital Equipment Corporation: DEC OpenVMS VAXBI DEC LANcontroller PDP VAXcluster DECnet ULTRIX VAXELN DECUS UNIBUS XMI DWMVA VAX FCC NOTICE: The equipment described in this manual generates, uses, and may emit radio frequency energy. The equipment has been type tested and found to comply with the limits for a Class A computing device pursuant to Subpart J of Part 15 of FCC Rules, which are designed to provide reasonable protection against such radio frequency interference when operated in a commercial environment. Operation of this equipment in a residential area may cause interference, in which case the user at his own expense may be required to take measures to correct the interference. iii Contents Preface ...................................................................................................... xi Chapter 1 Registers 1.1 KA7AA Registers ................................................................... 1­2 1.2 MS7AA Registers ................................................................. 1­31 1.3 I/O Port Registers ................................................................. 1­39 1.4 DWLMA Registers ............................................................... 1­46 Chapter 2 Addressing 2.1 VAX 10000 Block Diagram .................................................... 2­2 2.2 LSB Address Space ................................................................ 2­3 2.3 XMI Addresses ....................................................................... 2­6 2.4 VAXBI Addresses ................................................................... 2­7 Chapter 3 Console 3.1 Console Commands ................................................................ 3­2 3.2 Environment Variables .......................................................... 3­9 3.3 Device Naming Conventions ............................................... 3­12 3.4 Command Syntax ................................................................. 3­13 3.5 Boot Command ..................................................................... 3­15 3.6 Cdp Command ...................................................................... 3­18 3.7 Show Configuration Command ........................................... 3­19 3.8 Show Device Command ....................................................... 3­20 3.9 Show Network Command .................................................... 3­21 3.10 Show Power Command ........................................................ 3­22 iv Chapter 4 Diagnostics 4.1 Test Command ....................................................................... 4­2 4.2 Set Host Command · Running DUP­Based Diagnostics and Utilities .......................................................................... 4­10 4.3 Set Host Command · Running Diagnostics on a Remote XMI Adapter ......................................................................... 4­12 Chapter 5 FRU Locations 5.1 FRUs in the Main Cabinet .................................................... 5­2 5.2 FRUs in the Expander Cabinet ............................................. 5­6 5.3 Platform Cables ...................................................................... 5­8 5.4 FRUs in the XMI Plug­In Unit ............................................ 5­10 5.5 FRUs in the Disk Plug­In Unit ........................................... 5­12 5.6 FRUs in the Main Cabinet Battery Plug­In Units ............. 5­14 5.7 FRUs in the Battery Cabinet Plug­In Units ....................... 5­16 Chapter 6 Controls and Indicators 6.1 Control Panel .......................................................................... 6­2 6.2 TF85 Removable Media Device ............................................. 6­3 6.3 Cabinet Control Logic Module ............................................... 6­4 6.4 Power Regulator ..................................................................... 6­5 6.5 AC Input Box .......................................................................... 6­6 6.6 IOP Module ............................................................................. 6­7 6.7 KA7AA Processor Module ...................................................... 6­8 6.8 BA651 XMI PIU Power Regulators ..................................... 6­10 6.9 BA654 Disk PIU ................................................................... 6­12 6.10 DWLMA Module .................................................................. 6­14 Chapter 7 Restoring Corrupted ROMs 7.1 Restoring a Corrupted EEPROM .......................................... 7­2 7.2 Restoring Corrupted Firmware on an Adapter .................... 7­3 7.3 Restoring Corrupted Firmware on a CPU ............................ 7­7 Chapter 8 System Errors 8.1 Machine Check Frame ........................................................... 8­2 v 8.2 Machine Check Parse Tree .................................................... 8­5 8.3 Hard Error Parse Tree ......................................................... 8­12 8.4 Soft Error Parse Tree ........................................................... 8­20 8.5 I/O Port Parse Tree .............................................................. 8­21 8.6 DWLMA Parse Tree ............................................................. 8­23 Examples 2­1 Examining the Device Register of VAXBI Node 7 ............... 2­7 3­1 Boot Command · Booting from an InfoServer .................. 3­15 3­2 Cdp Command ...................................................................... 3­18 3­3 Show Configuration Command ........................................... 3­19 3­4 Show Device Command ....................................................... 3­20 3­5 Show Network Command .................................................... 3­21 3­6 Show Power Command ........................................................ 3­22 4­1 Test Command · System Test ............................................. 4­2 4­2 Test Command · Write/Read/Compare Test of All Disks Not Associated with Controller "a" ....................................... 4­4 4­3 Test Command · Destructive Exercising Selected, Then Aborted ................................................................................... 4­6 4­4 Output from Test Command · Quiet Qualifier Set ............ 4­6 4­5 Test Command · Detection of Memory Data Compare Error ....................................................................................... 4­7 4­6 Test Command · Use of Wildcard ....................................... 4­8 4­7 Test Command · Test All Devices Associated with XMI0 ....................................................................................... 4­9 4­8 Set Host Command · Running DUP­Based Diagnostics and Utilities .......................................................................... 4­10 4­9 Set Host Command · Running Diagnostics on a Remote XMI Adapter, Failing Case .................................................. 4­12 4­10 Set Host Command · Running Diagnostics on a Remote XMI Adapter, Passing Case ................................................. 4­13 7­1 Using the Build EEPROM Command to Restore a Corrupted EEPROM .............................................................. 7­2 7­2 Booting LFU .......................................................................... 7­3 7­3 LFU Display and Show Commands ...................................... 7­5 7­4 LFU Update Command .......................................................... 7­6 7­5 LFU Exit Command ............................................................... 7­6 7­6 Preparing the Source System to Restore Corrupted Firmware on a CPU ............................................................... 7­8 7­7 Running Kermit and Setting Parameters ............................ 7­8 7­8 Downline Loading Code to Corrupted FEPROMs ................ 7­9 vi Figures 1­1 LDEV · Device Register ....................................................... 1­3 1­2 LBER · Bus Error Register ................................................. 1­3 1­3 LCNR · Configuration Register .......................................... 1­4 1­4 LMMR07 · Memory Mapping Registers ........................... 1­4 1­5 LBESR03 · Bus Error Syndrome Registers ..................... 1­4 1­6 LBECR01 · Bus Error Command Registers ..................... 1­5 1­7 LIOINTR · I/O Interrupt Register ...................................... 1­5 1­8 LIPINTR · Interprocessor Interrupt Register .................... 1­5 1­9 LMODE · Mode Register ..................................................... 1­6 1­10 LMERR · Module Error Register ...................................... 1­7 1­11 LLOCK · Lock Address Register ......................................... 1­7 1­12 LDIAG · LSB Diagnostic Control Register ......................... 1­8 1­13 LTAGA · Tag Address Register .......................................... 1­8 1­14 LTAGW · Tag Write Data Register .................................... 1­8 1­15 LCON0,1 · Console Communication Registers .................. 1­9 1­16 LPERF · Performance Counter Control Register .............. 1­9 1­17 LCNTR0,1 · Performance Counter Registers ..................... 1­9 1­18 LMISSADDR · Last Miss Address Register ..................... 1­10 1­19 CPUID ·CPU Identification Register ............................... 1­14 1­20 ICCS · Interval Clock Control and Status Register ......... 1­15 1­21 NICR · Next Interval Count Register ............................... 1­15 1­22 ICR · Interval Count Register ........................................... 1­15 1­23 TODR · Time­of­Day Register ........................................... 1­15 1­24 MCESR · Machine Check Error Summary Register ....... 1­16 1­25 SID · System Identification Register ................................ 1­16 1­26 LMBOX · LSB Mailbox Register ....................................... 1­16 1­27 PCSCR · Patchable Control Store Control Register ........ 1­16 1­28 ECR · Ebox Control Register ............................................ 1­17 1­29 BIU_CTL · BIU Control Register ..................................... 1­17 1­30 DIAG_CTL · Diagnostic Control Register ........................ 1­18 1­31 BC_TAG · Diagnostic Control Register ............................ 1­18 1­32 BIU_STAT · BIU Status Register ..................................... 1­19 1­33 BIU_ADDR · BIU Address Register ................................. 1­19 1­34 FILL_SYND · Fill Syndrome Register ............................. 1­19 1­35 FILL_ADDR · Fill Address Register ................................. 1­20 1­36 BEDCC · Software ECC Register ..................................... 1­20 1­37 CHALT · Console Halt Register ........................................ 1­20 1­38 VMAR · VIC Memory Address Register ........................... 1­20 1­39 VTAG · VIC Tag Register .................................................. 1­21 1­40 VDATA · VIC Data Register ............................................. 1­21 1­41 ICSR · Ibox Control and Status Register ......................... 1­21 1­42 BPCR · Ibox Branch Prediction Control Register ............ 1­22 vii 1­43 MP0BR · Mbox P0 Base Register ..................................... 1­22 1­44 MP0LR · Mbox P0 Length Register .................................. 1­22 1­45 MP1BR · Mbox P1 Base Register ..................................... 1­23 1­46 MP1LR · Mbox P1 Length Register .................................. 1­23 1­47 MSBR · Mbox System Base Register ................................ 1­23 1­48 MSLR · Mbox System Length Register ............................ 1­23 1­49 MMAPEN · Mbox Map Enable Register .......................... 1­23 1­50 PAMODE · Physical Address Mode Register ................... 1­24 1­51 MMEADR · Memory Management Exception Address Register ................................................................................. 1­24 1­52 MMEPTE · Memory Management Exception PTE Address Register .................................................................. 1­24 1­53 MMESTS · Memory Management Exception Status Register ................................................................................. 1­24 1­54 TBADR · Translation Buffer Parity Address Register .... 1­25 1­55 TBSTS · Translation Buffer Parity Status Register ........ 1­25 1­56 PCADR · P­Cache Parity Address Register ..................... 1­25 1­57 PCSTS · P­Cache Parity Status Register ......................... 1­26 1­58 PCCTL · P­Cache Control Register .................................. 1­26 1­59 PCTAG · P­Cache Tag Registers ...................................... 1­26 1­60 PCDAP · P­Cache Data Parity Registers ......................... 1­27 1­61 Gbus$WHAMI Register ....................................................... 1­27 1­62 Gbus$LEDs Register ............................................................ 1­28 1­63 Gbus$PMask Register ......................................................... 1­28 1­64 Gbus$Intr Register .............................................................. 1­29 1­65 Gbus$Halt Register ............................................................. 1­29 1­66 Gbus$LSBRST Register ...................................................... 1­29 1­67 Gbus$Misc Register ............................................................. 1­30 1­68 Gbus$RMode Register ......................................................... 1­30 1­69 Gbus$LTagRW Register ...................................................... 1­30 1­70 LDEV · Device Register ..................................................... 1­32 1­71 LBER · Bus Error Register ............................................... 1­32 1­72 LCNR · Configuration Register ........................................ 1­33 1­73 IBR · Information Base Repair Register .......................... 1­33 1­74 LBESR03 · Error Syndrome Registers ........................... 1­33 1­75 LBECR0, 1 · Bus Error Command Registers ................... 1­34 1­76 MCR · Memory Configuration Register ............................ 1­34 1­77 AMR · Address Mapping Register .................................... 1­34 1­78 MSTR0, 1 · Memory Self­Test Registers .......................... 1­35 1­79 FADR · Failing Address Register ..................................... 1­35 1­80 MERA · Memory Error Register A ................................... 1­35 1­81 MSYNDA · Memory Error Syndrome Register A ............ 1­36 1­82 MDRA · Memory Diagnostic Register A ........................... 1­36 1­83 MCBSA · Memory Check Bit Substitute Register A ....... 1­36 viii 1­84 MERB · Memory Error Register B ................................... 1­37 1­85 MSYNDB · Memory Error Syndrome Register B ............ 1­37 1­86 MDRB · Memory Diagnostic Register B ........................... 1­37 1­87 MCBSB · Memory Check Bit Substitute Register B ....... 1­38 1­88 LDEV · Device Register ..................................................... 1­40 1­89 LBER · Bus Error Register ............................................... 1­41 1­90 LCNR · Configuration Register ........................................ 1­41 1­91 IBR · Information Base Repair Register .......................... 1­42 1­92 LMMR07 · Memory Mapping Registers ......................... 1­42 1­93 LBESR03 · Bus Error Syndrome Registers ................... 1­42 1­94 LBECR0,1 · Bus Error Command Registers .................... 1­43 1­95 LILID03 · Interrupt Level 03 IDENT Registers .......... 1­43 1­96 LCPUMASK · CPU Interrupt Mask Register .................. 1­43 1­97 LMBPR03 · Mailbox Pointer Registers .......................... 1­43 1­98 IPCNSE · I/O Port Chip Node­Specific Error Register .... 1­44 1­99 IPCVR · I/O Port Chip Vector Register ............................ 1­44 1­100 IPCMSR · I/O Port Chip Mode Selection Register ........... 1­44 1­101 IPCHST · I/O Port Chip Hose Status Register ................ 1­45 1­102 IPCDR · I/O Port Chip Diagnostic Register ..................... 1­45 1­103 LDIAG · Diagnostic Register ............................................ 1­46 1­104 IMSK · Interrupt Mask Register ...................................... 1­47 1­105 LEVR · Error Vector Register ........................................... 1­47 1­106 LERR · Error Register ....................................................... 1­47 1­107 LGPR · General Purpose Register .................................... 1­48 1­108 IPR1 · Interrupt Pending Register 1 ................................ 1­48 1­109 IPR2 · Interrupt Pending Register 2 ................................ 1­48 1­110 IIPR · Interrupt in Progress Register ............................... 1­48 1­111 XDEV · Device Register .................................................... 1­49 1­112 XBER · Bus Error Register ............................................... 1­50 1­113 XFADR · Failing Address Register ................................... 1­51 1­114 IBR · Information Base Repair Register .......................... 1­51 1­115 XFAER · Failing Address Extension Register ................. 1­51 2­1 VAX 10000 Block Diagram .................................................... 2­2 2­2 Virtual Address Space Layout ............................................... 2­3 2­3 Physical Address Space Layouts ........................................... 2­3 5­1 Main Cabinet (Front) Showing FRU Locations .................... 5­2 5­2 Main Cabinet (Rear) Showing FRU Locations ..................... 5­4 5­3 Expander Cabinet Showing FRU Locations ......................... 5­6 5­4 Platform Cabinet (Rear and Front) Showing Cables ........... 5­8 5­5 XMI Plug­In Unit (Front) Showing FRU Locations ........... 5­10 5­6 Disk Plug­In Unit (Front) Showing FRU Locations ........... 5­12 5­7 Main Cabinet Battery Plug­In Units (Rear) Showing FRU Locations ...................................................................... 5­14 5­8 Battery Cabinet Plug­In Units (Rear) Showing FRU Locations ............................................................................... 5­16 ix 6­1 Control Panel .......................................................................... 6­2 6­2 TF85 Controls and Indicators ............................................... 6­3 6­3 CCL Module LEDs ................................................................. 6­4 6­4 Power Regulator LEDs .......................................................... 6­5 6­5 AC Input Box · Indicators on Circuit Breaker ................... 6­6 6­6 IOP (E2044­AA) Module LED ............................................... 6­7 6­7 Processor (E2045) LEDs After Self­Test ............................... 6­8 6­8 XMI PIU Power Regulators ................................................. 6­10 6­9 Disk Brick Control Panel ..................................................... 6­12 6­10 DWLMA (T2028­AA) Module LEDs .................................... 6­14 8­1 Machine Check Exception Frame ......................................... 8­2 8­2 Machine Check Parse Tree .................................................... 8­5 8­3 Hard Error Parse Tree ......................................................... 8­12 8­4 Soft Error Parse Tree ........................................................... 8­20 8­5 IOP Error Parse Tree ........................................................... 8­21 8­6 DWLMA Parse Tree ............................................................. 8­23 Tables 1 VAX 10000 Documentation .................................................... xii 2 Related Documents ................................................................ xiv 1­1 LSB Required Registers ......................................................... 1­2 1­2 KA7AA­Specific Registers ..................................................... 1­6 1­3 KA7AA Internal Processor Registers .................................. 1­11 1­4 Gbus Registers ..................................................................... 1­27 1­5 MS7AA Registers ................................................................. 1­31 1­6 I/O Port Registers ................................................................. 1­39 1­7 LSB Registers ....................................................................... 1­46 1­8 XMI Registers ....................................................................... 1­49 2­1 Address Mapping from 30­Bit Mode to 32­Bit Mode ............ 2­4 2­2 LSB Node Base Addresses ..................................................... 2­4 2­3 Device Type Codes ................................................................. 2­5 2­4 XMI Node Addresses .............................................................. 2­6 2­5 Base Addresses of VAXBI Nodes ........................................... 2­8 2­6 Address Offsets of VAXBI Registers ..................................... 2­9 3­1 Console Commands ................................................................ 3­2 3­2 Boot Command Options ......................................................... 3­3 3­3 Cdp Command Options .......................................................... 3­4 3­4 Clear EEPROM Command Options ...................................... 3­4 3­5 Create Command Option ....................................................... 3­5 3­6 Deposit and Examine Command Options ............................. 3­5 3­7 Set EEPROM Command Options .......................................... 3­6 3­8 Set Host Command Options .................................................. 3­6 x 3­9 Show EEPROM Command Options ...................................... 3­6 3­10 Show Power Command Options ............................................ 3­7 3­11 Test Command Options ......................................................... 3­7 3­12 Update Command Options .................................................... 3­8 3­13 Environment Variables .......................................................... 3­9 3­14 Device Name Fields ............................................................. 3­12 3­15 Console Special Characters ................................................. 3­14 3­16 Sample Boot Commands ...................................................... 3­17 3­17 Abbreviations Used in Show Power Command Output ..... 3­23 6­1 Control Panel Indicator Lights .............................................. 6­2 6­2 TF85 Lights ............................................................................ 6­3 6­3 CCL Module LEDs ................................................................. 6­4 6­4 Power Regulator Lights ......................................................... 6­5 6­5 AC Input Box · Indicators on Circuit Breaker ................... 6­6 6­6 IOP (E2044­AA) Module LED ............................................... 6­7 6­7 Processor (E2045) LEDs After Self­Test ............................... 6­9 6­8 Self­Test LEDs Indicating Defective DC­to­DC Converter ................................................................................ 6­9 6­9 XMI PIU Power Regulator Lights (Regulators A and B) ... 6­11 6­10 XMI PIU Power Switches (Regulator B) ............................. 6­11 6­11 Disk Brick Controls and Indicators .................................... 6­13 6­12 DWLMA (T2028­AA) Module LEDs .................................... 6­14 8­1 Machine Check Stack Frame Fields ..................................... 8­3 8­2 Machine Check Codes in the Stack Frame ........................... 8­4 xi Preface Intended Audience This manual is written for the Digital service engineer. Document Structure This manual has eight chapters: · Chapter 1, Registers, lists the registers in this system and provides an illustration of each. · Chapter 2, Addressing, provides information on address space lay­ out, addresses, and device types. · Chapter 3, Console, contains a list of the console commands, syntax, and error messages. · Chapter 4, Diagnostics, shows examples of running diagnostics on adapters and device controllers. · Chapter 5, FRU Locations, identifies the field­replaceable units in the platform. · Chapter 6, Controls and Indicators, discusses the controls and in­ dicators on various components of the system. · Chapter 7, Restoring Corrupted ROMs, provides instructions for restoring corrupted EEPROMs and for updating corrupted firmware. · Chapter 8, System Errors, includes the machine check frame and the system parse trees. xii Conventions Used in This Document The text shown in command syntax uses these conventions: · Bold text indicates elements to be typed at the terminal. · Brackets ([]) indicate that an element is optional. · Braces ({}) indicate a choice from the enclosed list. · Angle brackets (<>) indicate that the enclosed text is not a literal de­ piction of the element but instead a reference to the kind of item that can appear in that position. Icons such as those shown below are used in illustrations for designating part placement in the system described. A shaded area in the icon shows the location of the component or part being discussed. Document Titles Table 1 lists the books in the VAX 10000 documentation set. Table 2 lists other documents that you may find useful. Table 1 VAX 10000 Documentation Title Order Number Installation Kit EK1000ADK Site Preparation Guide EK1000ASP Installation Guide EK100EAIN Hardware User Information Kit EK1001ADK Operations Manual EK1000AOP Basic Troubleshooting EK1000ATS xiii Table 1 VAX 10000 Documentation (Continued) Title Order Number Service Information Kit EK1002ADK Pocket Service Guide EK1000APG Advanced Troubleshooting EK1001ATS Platform Service Manual EK1000ASV System Service Manual EK1002ASV Reference Manuals Console Reference Manual EK70C0BTM KA7AA CPU Technical Manual EKKA7AATM MS7AA Technical Manual EKMS7AATM I/O System Technical Manual EK70I0ATM Platform Technical Manual EK7000ATM Upgrade Manuals KA7AA CPU Installation Card EKKA7AAIN MS7AA Memory Installation Card EKMS7AAIN DWLMA XMI PIU Installation Guide EKDWLMAIN H7237 Battery PIU Installation Guide EKH7237IN H7263 Power Regulator Installation Card EKH7263IN BA654 Disk PIU Installation Guide EKBA654IN DWMBB VAXBI PIU Installation Guide EKDWMBBIN Removable Media Installation Guide EKTFRRDIN xiv Table 2 Related Documents Title Order Number General Site Preparation Site Environmental Preparation Guide EKCSEPGMA System I/O Options CIXCD Interface User Guide EKCIXCDUG DEC FDDIcontroller 400 Installation/Problem Solving EKDEMFAIP DEC LANcontroller 400 Installation Guide EKDEMNAIN DEC LANcontroller 400 Technical Manual EKDEMNATM DSSI VAXcluster Installation and Troubleshoot­ ing Manual EK410AAMG InfoServer 150 Installation and Owner's Guide EKINFSVOM KFMSA Module Installation and User Manual EKKFMSAIM KFMSA Module Service Guide EKKFMSASV RF Series Integrated Storage Element User Guide EKRF72DUG TF85 Cartridge Tape Subsystem Owner's Manual EKOTF85OM Operating System Manuals VMS Upgrade and Installation Supplement: VAX 7000600 and VAX 10000600 Series AAPRAHATE VMS Network Control Program Manual AALA50ATE VAXclusters and Networking HSC Installation Manual EKHSCMNIN SC008 Star Coupler User's Guide EKSC008UG VAX Volume Shadowing Manual AAPBTVATE Peripherals Installing and Using the VT420 Video Terminal EKVT420UG LA75 Companion Printer Installation and User Guide EKLA75XUG Registers 1­1 Chapter 1 Registers This chapter is a compilation of the major registers in components of the VAX 10000 system. Each section consists of a list of the registers in the component including register name, mnemonic, and address and illustra­ tions of the major registers. Sections include: · KA7AA Registers · LSB Required Registers · CPU­Specific Registers · Internal Processor Registers · Gbus Registers · MS7AA Registers · I/O Port Registers · DWLMA Registers · LSB Registers · XMI Registers 1­2 Registers 1.1 KA7AA Registers Table 1­1 LSB Required Registers Mnemonic Register Name Byte Offset LDEV Device BB 1 + 0000 LBER Bus Error BB + 0040 LCNR Configuration BB + 0080 LMMR0 Memory Mapping 0 BB + 0200 LMMR1 Memory Mapping 1 BB + 0240 LMMR2 Memory Mapping 2 BB + 0280 LMMR3 Memory Mapping 3 BB + 02C0 LMMR4 Memory Mapping 4 BB + 0300 LMMR5 Memory Mapping 5 BB + 0340 LMMR6 Memory Mapping 6 BB + 0380 LMMR7 Memory Mapping 7 BB + 03C0 LBESR0 Bus Error Syndrome 0 BB + 0600 LBESR1 Bus Error Syndrome 1 BB + 0640 LBESR2 Bus Error Syndrome 2 BB + 0680 LBESR3 Bus Error Syndrome 3 BB + 06C0 LBECR0 Bus Error Command 0 BB + 0700 LBECR1 Bus Error Command 1 BB + 0740 LIOINTR I/O Interrupt BSB2 + 0000 LIPINTR Interprocessor Interrupt BSB + 0040 1 BB is the node space base address of the CPU module in hex. 2 BSB is the broadcast space base address, which is FE00 0000. Registers 1­3 Figure 1­1 LDEV · Device Register Figure 1­2 LBER · Bus Error Register 1­4 Registers Figure 1­3 LCNR · Configuration Register Figure 1­4 LMMR07 · Memory Mapping Registers Figure 1­5 LBESR03 · Bus Error Syndrome Registers Registers 1­5 Figure 1­6 LBECR01 · Bus Error Command Registers Figure 1­7 LIOINTR · I/O Interrupt Register Figure 1­8 LIPINTR · Interprocessor Interrupt Register 1­6 Registers Table 1­2 KA7AA­Specific Registers Figure 1­9 LMODE · Mode Register Mnemonic Register Name Byte Offset LMODE Mode BB + 0C00 LMERR Module Error BB + 0C40 LLOCK Lock Address BB + 0C80 LDIAG LSB Diagnostic Control BB + 0D00 LTAGA Tag Address BB + 0D40 LTAGW Tag Write Data BB + 0D80 LCON0 Console Communication 0 BB + 0E00 LCON1 Console Communication 1 BB + 0E40 LPERF Performance Counter Control BB + 0F00 LCNTR0 Performance Counter 0 BB + 0F40 LCNTR1 Performance Counter 1 BB + 0F80 LMISSADDR Last Miss Address BB + 0FC0 Registers 1­7 Figure 1­10 LMERR · Module Error Register Figure 1­11 LLOCK · Lock Address Register 1­8 Registers Figure 1­12 LDIAG · LSB Diagnostic Control Register Figure 1­13 LTAGA · Tag Address Register Figure 1­14 LTAGW · Tag Write Data Register Registers 1­9 Figure 1­15 LCON0,1 · Console Communication Registers Figure 1­16 LPERF · Performance Counter Control Register Figure 1­17 LCNTR0,1 · Performance Counter Registers 1­10 Registers Figure 1­18 LMISSADDR · Last Miss Address Register Registers 1­11 Table 1­3 KA7AA Internal Processor Registers Mnemonic Register Name Address Dec Hex Type KSP Kernel Stack Pointer 0 0 R/W ESP Executive Stack Pointer 1 1 R/W SSP Supervisor Stack Pointer 2 2 R/W USP User Stack Pointer 3 3 R/W ISP Interrupt Stack Pointer 4 4 R/W P0BR P0 Base 8 8 R/W P0LR P0 Length 9 9 R/W P1BR P1 Base 10 A R/W P1LR P1 Length 11 B R/W SBR System Base 12 C R/W SLR System Length 13 D R/W CPUID CPU Identification 1 14 E RO PCBB Process Control Block Base 16 10 R/W SCBB System Control Block Base 17 11 R/W IPL Interrupt Priority Level 1 18 12 R/W ASTLVL AST Level 1 19 13 R/W SIRR Software Interrupt Request 20 14 WO SISR Software Interrupt Summary 1 21 15 R/W ICCS Interval Clock Control/Status 1 24 18 R/W NICR Next Interval Count 25 19 WO ICR Interval Count 26 1A RO TODR Time­of­Day 27 1B R/W MCESR Machine Check Error Summary 38 26 WO SAVPC Console Saved PC 42 2A RO SAVPSL Console Saved PSL 43 2B RO 1 Initialized on reset. 1­12 Registers Table 1­3 KA7AA Internal Processor Registers (Continued) Mnemonic Register Name Address Dec Hex Type MAPEN Memory Management Enable 1 56 38 R/W TBIA Translation Buffer Invalidate All 57 39 WO TBIS Translation Buffer Invalidate Single 58 3A WO PME Performance Monitor Enable 1 61 3D R/W SID System Identification 62 3E RO TBCHK Translation Buffer Check 63 3F WO LMBOX Mailbox 121 79 R/W INTSYS Interrupt System Status 2 122 7A R/W PMFCNT Performance Monitoring Facility Count 123 7B R/W PCSCR Patchable Control Store Control2 124 7C R/W ECR Ebox Control 125 7D R/W MTBTAG Mbox TB Tag Fill 2 126 7E WO MTBPTE Mbox TB PTE Fill 2 127 7F WO BIU_CTL BIU Control 160 A0 WO DIAG_CTL Diagnostic Control 161 A1 WO BC_TAG B­Cache Error Tag 162 A2 RO BIU_STAT BIU Status 164 A4 W1C BIU_ADDR BIU Address 166 A6 RO FILL_SYND Fill Syndrome 168 A8 RO FILL_ADDR Fill Address 170 AA RO IPR_STR_ COND STxC Pass Fail/CEFSTS 172 AC R/W 1 Initialized on reset. 2 Testability and diagnostic use only; not for software use in normal operation. Registers 1­13 Table 1­3 KA7AA Internal Processor Registers (Continued) Mnemonic Register Name Address Dec Hex Type BEDECC Software ECC 174 AE WO CHALT Console Halt 176 B0 R/W SIO Serial I/O 178 B2 R/W SOE­IE SROM_OE_Serial I.E. 180 B4 WO QW_PACK Pack to QW 184 B8 WO CLR_IO_ PACK Clear I/O Pack 185 B9 WO VMAR VIC Memory Address 208 D0 R/W VTAG VIC Tag 209 D1 R/W VDATA VIC Data 210 D2 R/W ICSR Ibox Control and Status 211 D3 R/W BPCR Ibox Branch Prediction Control2 212 D4 R/W BPC Ibox Backup PC 214 D6 RO BPCUNW Ibox Backup PC with RLOG Unwind 3 215 D7 RO MP0BR Mbox P0 Base 2 224 E0 R/W MP0LR Mbox P0 Length 2 225 E1 R/W MP1BR Mbox P1 Base 2 226 E2 R/W MP1LR Mbox P1 Length 2 227 E3 R/W MSBR Mbox System Base 2 228 E4 R/W MSLR Mbox System Length 2 229 E5 R/W MMAPEN Mbox Map Enable 2 230 E6 R/W PAMODE Physical Address Mode 231 E7 R/W MMEADR Memory Management Exception Address 232 E8 RO 2 Testability and diagnostic use only; not for software use in normal operation. 3 Chip use only; not for software use. 1­14 Registers Table 1­3 KA7AA Internal Processor Registers (Continued) Figure 1­19 CPUID ·CPU Identification Register Mnemonic Register Name Address Dec Hex Type MMEPTE Memory Management Excep­ tion PTE Address 233 E9 RO MMESTS Memory Management Excep­ tion Status 234 EA RO TBADR Translation Buffer Parity Ad­ dress 236 EC RO TBSTS Translation Buffer Parity Status 237 ED R/W PCADR P­Cache Parity Address 242 F2 RO PCSTS P­Cache Parity Status 244 F4 R/W PCCTL P­Cache Control 248 F8 R/W PCTAG P­Cache Tag 0180 0000 to 0180 1FE0 (hex) R/W PCDAP P­Cache Data Parity 01C0 0000 to 01C0 1FF8 (hex) R/W Registers 1­15 Figure 1­20 ICCS · Interval Clock Control and Status Register Figure 1­21 NICR · Next Interval Count Register Figure 1­22 ICR · Interval Count Register Figure 1­23 TODR · Time­of­Day Register 1­16 Registers Figure 1­24 MCESR · Machine Check Error Summary Register Figure 1­25 SID · System Identification Register Figure 1­26 LMBOX · LSB Mailbox Register Figure 1­27 PCSCR · Patchable Control Store Control Register Registers 1­17 Figure 1­28 ECR · Ebox Control Register Figure 1­29 BIU_CTL · BIU Control Register 1­18 Registers Figure 1­30 DIAG_CTL · Diagnostic Control Register Figure 1­31 BC_TAG · Diagnostic Control Register Registers 1­19 Figure 1­32 BIU_STAT · BIU Status Register Figure 1­33 BIU_ADDR · BIU Address Register Figure 1­34 FILL_SYND · Fill Syndrome Register 1­20 Registers Figure 1­35 FILL_ADDR · Fill Address Register Figure 1­36 BEDCC · Software ECC Register Figure 1­37 CHALT · Console Halt Register Figure 1­38 VMAR · VIC Memory Address Register Registers 1­21 Figure 1­39 VTAG · VIC Tag Register Figure 1­40 VDATA · VIC Data Register Figure 1­41 ICSR · Ibox Control and Status Register 1­22 Registers Figure 1­42 BPCR · Ibox Branch Prediction Control Register Figure 1­43 MP0BR · Mbox P0 Base Register Figure 1­44 MP0LR · Mbox P0 Length Register Registers 1­23 Figure 1­45 MP1BR · Mbox P1 Base Register Figure 1­46 MP1LR · Mbox P1 Length Register Figure 1­47 MSBR · Mbox System Base Register Figure 1­48 MSLR · Mbox System Length Register Figure 1­49 MMAPEN · Mbox Map Enable Register 1­24 Registers Figure 1­50 PAMODE · Physical Address Mode Register Figure 1­51 MMEADR · Memory Management Exception Address Register Figure 1­52 MMEPTE · Memory Management Exception PTE Address Register Figure 1­53 MMESTS · Memory Management Exception Status Register Registers 1­25 Figure 1­54 TBADR · Translation Buffer Parity Address Register Figure 1­55 TBSTS · Translation Buffer Parity Status Register Figure 1­56 PCADR · P­Cache Parity Address Register 1­26 Registers Figure 1­57 PCSTS · P­Cache Parity Status Register Figure 1­58 PCCTL · P­Cache Control Register Figure 1­59 PCTAG · P­Cache Tag Registers Registers 1­27 Figure 1­60 PCDAP · P­Cache Data Parity Registers Table 1­4 Gbus Registers Figure 1­61 Gbus$WHAMI Register Register Address Type Gbus$WHAMI F700 0000 RO Gbus$LEDs F700 0040 R/W Gbus$PMask F700 0080 R/W Gbus$Intr F700 00C0 R/W Gbus$Halt F700 0100 R/W Gbus$LSBRST F700 0140 R/W Gbus$Misc F700 0180 R/W Gbus$RMode F780 0000 R/W Gbus$LTagRW F780 0100 R/W 1­28 Registers Figure 1­62 Gbus$LEDs Register Figure 1­63 Gbus$PMask Register Registers 1­29 Figure 1­64 Gbus$Intr Register Figure 1­65 Gbus$Halt Register Figure 1­66 Gbus$LSBRST Register 1­30 Registers Figure 1­67 Gbus$Misc Register Figure 1­68 Gbus$RMode Register Figure 1­69 Gbus$LTagRW Register Registers 1­31 1.2 MS7AA Registers Table 1­5 MS7AA Registers Mnemonic Register Name Address Byte Offset LDEV Device BB + 0000 LBER Bus Error BB + 0040 LCNR Configuration BB + 0080 IBR Information Base Repair BB + 00C0 LBESR0 Error Syndrome 0 BB + 0600 LBESR1 Error Syndrome 1 BB + 0640 LBESR2 Error Syndrome 2 BB + 0680 LBESR3 Error Syndrome 3 BB + 06C0 LBECR0 Error Command 0 BB + 0700 LBECR1 Error Command 1 BB + 0740 MCR Memory Configuration BB + 2000 AMR Address Mapping BB + 2040 MSTR0 Memory Self­Test 0 BB + 2080 MSTR1 Memory Self­Test 1 BB + 20C0 FADR Failing Address BB + 2100 MERA Memory Error A BB + 2140 MSYNDA Memory Error Syndrome A BB + 2180 MDRA Memory Diagnostic A BB + 21C0 MCBSA Memory Check Bit Substitute A BB + 2200 MERB Memory Error B BB + 4140 MSYNDB Memory Error Syndrome B BB + 4180 MDRB Memory Diagnostic B BB + 41C0 MCBSB Memory Check Bit Substitute B BB + 4200 1­32 Registers Figure 1­70 LDEV · Device Register Figure 1­71 LBER · Bus Error Register Registers 1­33 Figure 1­72 LCNR · Configuration Register Figure 1­73 IBR · Information Base Repair Register Figure 1­74 LBESR03 · Error Syndrome Registers 1­34 Registers Figure 1­75 LBECR0, 1 · Bus Error Command Registers Figure 1­76 MCR · Memory Configuration Register Figure 1­77 AMR · Address Mapping Register Registers 1­35 Figure 1­78 MSTR0, 1 · Memory Self­Test Registers Figure 1­79 FADR · Failing Address Register Figure 1­80 MERA · Memory Error Register A 1­36 Registers Figure 1­81 MSYNDA · Memory Error Syndrome Register A Figure 1­82 MDRA · Memory Diagnostic Register A Figure 1­83 MCBSA · Memory Check Bit Substitute Register A Registers 1­37 Figure 1­84 MERB · Memory Error Register B Figure 1­85 MSYNDB · Memory Error Syndrome Register B Figure 1­86 MDRB · Memory Diagnostic Register B 1­38 Registers Figure 1­87 MCBSB · Memory Check Bit Substitute Register B Registers 1­39 1.3 I/O Port Registers Table 1­6 I/O Port Registers Mnemonic Register Name Physical Address Software Address LDEV Device 50 0000 A00 0000 LBER Bus Error 50 0002 A00 0040 LCNR Configuration 50 0004 A00 0080 IBR Information Base Repair 50 0006 A00 00C0 LMMR0 Memory Mapping 0 50 0010 A00 0200 LMMR1 Memory Mapping 1 50 0012 A00 0240 LMMR2 Memory Mapping 2 50 0014 A00 0280 LMMR3 Memory Mapping 3 50 0016 A00 02C0 LMMR4 Memory Mapping 4 50 0018 A00 0300 LMMR5 Memory Mapping 5 50 001A A00 0340 LMMR6 Memory Mapping 6 50 001C A00 0380 LMMR7 Memory Mapping 7 50 001E A00 03C0 LBESR0 Bus Error Syndrome 0 50 0030 A00 0600 LBESR1 Bus Error Syndrome 1 50 0032 A00 0640 LBESR2 Bus Error Syndrome 2 50 0034 A00 0680 LBESR3 Bus Error Syndrome 3 50 0036 A00 06C0 LBECR0 Bus Error Command 0 50 0038 A00 0700 LBECR1 Bus Error Command 1 50 003A A00 0740 LILID0 Interrupt Level 0 IDENT 50 0050 A00 0A00 LILID1 Interrupt Level 1 IDENT 50 0052 A00 0A40 LILID2 Interrupt Level 2 IDENT 50 0054 A00 0A80 LILID3 Interrupt Level 3 IDENT 50 0056 A00 0AC0 LCPUMASK CPU Interrupt Mask 50 0058 A00 0B00 1­40 Registers Table 1­6 I/O Port Registers (Continued) Figure 1­88 LDEV · Device Register Mnemonic Register Name Physical Address Software Address LMBPR0 Mailbox Pointer 0 50 0060 A00 0C00 LMBPR1 Mailbox Pointer 1 50 0062 A00 0C00 LMBPR2 Mailbox Pointer 2 50 0064 A00 0C00 LMBPR3 Mailbox Pointer 3 50 0066 A00 0C00 IPCNSE I/O Port Chip Node­Specific Error 50 0100 A00 2000 IPCVR I/O Port Chip Vector 50 0102 A00 2040 IPCMSR I/O Port Chip Mode Selection 50 0104 A00 2080 IPCHST I/O Port Chip Hose Status 50 0106 A00 20C0 IPCDR I/O Port Chip Diagnostic 50 0108 A00 2100 Registers 1­41 Figure 1­89 LBER · Bus Error Register Figure 1­90 LCNR · Configuration Register 1­42 Registers Figure 1­91 IBR · Information Base Repair Register Figure 1­92 LMMR07 · Memory Mapping Registers Figure 1­93 LBESR03 · Bus Error Syndrome Registers Registers 1­43 Figure 1­94 LBECR0,1 · Bus Error Command Registers Figure 1­95 LILID03 · Interrupt Level 03 IDENT Registers Figure 1­96 LCPUMASK · CPU Interrupt Mask Register Figure 1­97 LMBPR03 · Mailbox Pointer Registers 1­44 Registers Figure 1­98 IPCNSE · I/O Port Chip Node­Specific Error Register Figure 1­99 IPCVR · I/O Port Chip Vector Register Figure 1­100 IPCMSR · I/O Port Chip Mode Selection Register Registers 1­45 Figure 1­101 IPCHST · I/O Port Chip Hose Status Register Figure 1­102 IPCDR · I/O Port Chip Diagnostic Register 1­46 Registers 1.4 DWLMA Registers Table 1­7 LSB Registers Figure 1­103 LDIAG · Diagnostic Register Mnemonic Register Name Address LDIAG Diagnostic BB + 40 IMSK Interrupt Mask BB + 44 LEVR Error Vector BB + 48 LERR Error BB + 4C LGPR General Purpose BB + 50 IPR1 Interrupt Pending 1 BB + 54 IPR2 Interrupt Pending 2 BB + 58 IIPR Interrupt in Progress BB + 5C Registers 1­47 Figure 1­104 IMSK · Interrupt Mask Register Figure 1­105 LEVR · Error Vector Register Figure 1­106 LERR · Error Register 1­48 Registers Figure 1­107 LGPR · General Purpose Register Figure 1­108 IPR1 · Interrupt Pending Register 1 Figure 1­109 IPR2 · Interrupt Pending Register 2 Figure 1­110 IIPR · Interrupt in Progress Register Registers 1­49 Table 1­8 XMI Registers Figure 1­111 XDEV · Device Register Mnemonic Register Name Address XDEV Device BB + 00 XBER Bus Error BB + 04 XFADR Failing Address BB + 08 IBR Information Base Repair BB + 10 XFAER Failing Address Extension BB + 2C 1­50 Registers Figure 1­112 XBER · Bus Error Register Registers 1­51 Figure 1­113 XFADR · Failing Address Register Figure 1­114 IBR · Information Base Repair Register Figure 1­115 XFAER · Failing Address Extension Register Addressing 2­1 Chapter 2 Addressing This chapter includes an overview of the VAX 10000 system and address­ ing information for the buses used in the system. Sections include: · VAX 10000 Block Diagram · LSB Address Space · XMI Addresses · VAXBI Addresses 2­2 Addressing 2.1 VAX 10000 Block Diagram Figure 2­1 VAX 10000 Block Diagram Addressing 2­3 2.2 LSB Address Space Figure 2­2 Virtual Address Space Layout Figure 2­3 Physical Address Space Layouts Figure 2­3 shows 30­bit addressing mode on the left and 32­bit addressing mode on the right. 2­4 Addressing Table 2­1 Address Mapping from 30­Bit Mode to 32­Bit Mode Table 2­2 LSB Node Base Addresses 30­Bit Mode Address 32­Bit Mode Address 0000 0000 · 1FFF FFFF 0000 0000 · 1FFF FFFF 2000 0000 · 3FFF FFFF E000 0000 · FFFF FFFF Node Module Base Physical Address (BB) 0 CPU 0 F800 0000 1 Processor or memory F840 0000 2 Processor or memory F880 0000 3 Processor or memory F8C0 0000 4 Memory F900 0000 5 Memory F940 0000 6 Memory F980 0000 7 Memory F9C0 0000 8 IOP FA00 0000 Broadcast Space Base BSB FE00 0000 For more information: KA7AA CPU Technical Manual Addressing 2­5 Table 2­3 Device Type Codes Device Code (hex) KA7AA 8002 MS7AA 4000 IOP 2000 DWLMA 102A CIXCD 0C05 DEMFA 0823 DEMNA 0C03 DWMBB 2002 KDM70 0C22 KFMSA 0810 2­6 Addressing 2.3 XMI Addresses Table 2­4 XMI Node Addresses Node Mailbox Base Physical Address (BB) XMI Base Physical Address (BB) 1 6180 0000 80 0180 0000 2 6188 0000 80 0188 0000 3 6190 0000 80 0190 0000 4 6198 0000 80 0198 0000 5 61A0 0000 80 01A0 0000 6 61A8 0000 80 01A8 0000 7 61B0 0000 80 01B0 0000 8 61B8 0000 80 01B8 0000 9 61C0 0000 80 01C0 0000 10 61C8 0000 80 01C8 0000 11 61D0 0000 80 01D0 0000 12 61D8 0000 80 01D8 0000 13 61E0 0000 80 01E0 0000 14 61E8 0000 80 01E8 0000 Addressing 2­7 2.4 VAXBI Addresses To examine a VAXBI register from the VAX 10000 console (see Example 2­1), you need three pieces of information: 1. The XMI number (03) to which the VAXBI bus is connected. 2. The base address of the VAXBI node (see Table 2­5). 3. The offset of the VAXBI register to be examined (see Table 2­6). The address of the register to be examined is expressed in this form: xmin:220xxyyy where: n = the XMI number xx = the base address of the VAXBI node yyy = the address offset of the VAXBI register To calculate the address of the VAXBI register, add 2200 0000 plus the base address of the VAXBI node (Table 2­5) plus the address offset of the VAXBI register (Table 2­6). NOTE: You must look at the node ID plug on the backplane of the VAXBI card cage to determine the node ID of the VAXBI option. Example 2­1 Examining the Device Register of VAXBI Node 7 >>> e xmi1:2200E000 xmi1: 2200E000 131C010E >>> 2­8 Addressing Table 2­5 Base Addresses of VAXBI Nodes Node ID Base Address 0 0000 0000 1 0000 2000 2 0000 4000 3 0000 6000 4 0000 8000 5 0000 A000 6 0000 C000 7 0000 E000 8 0001 0000 9 0001 2000 A 0001 4000 B 0001 6000 C 0001 8000 D 0001 A000 E 0001 C000 F 0001 E000 Addressing 2­9 Table 2­6 Address Offsets of VAXBI Registers Mnemonic Register Name Address Offset DTYPE Device bb 1 + 00 VAXBICSR VAXBI Control and Status bb + 04 BER Bus Error bb + 08 EINTRSCR Error Interrupt Control bb + 0C INTRDES Interrupt Destination bb + 10 IPINTRMSK IPINTR Mask bb + 14 FIPSDES Force­Bit IPINTR/STOP Destination bb + 18 IPINTRSRC IPINTR Source bb + 1C SADR Starting Address bb + 20 EADR Ending Address bb + 24 BCICSR BCI Control and Status bb + 28 WSTAT Write Status bb + 2C FIPSCMD Force­Bit IPINTR/STOP Command bb + 30 UINTRCSR User Interface Interrupt Control bb + 40 GPR0 General Purpose Register 0 bb + F0 GPR1 General Purpose Register 1 bb + F4 GPR2 General Purpose Register 2 bb + F8 GPR3 General Purpose Register 3 bb + FC SOSR Slave­Only Status bb + 100 RXCD Receive Console Data bb + 200 1 bb is the base address of the VAXBI node (the address of the first location of the nodespace). Console 3­1 Chapter 3 Console This chapter contains an overview of the console command set and com­ mand syntax. It includes a section on device naming and examples of the use of selected commands. Sections include: · Console Commands · Environment Variables · Device Naming Conventions · Command Syntax · Boot Command · Cdp Command · Show Configuration Command · Show Device Command · Show Network Command · Show Power Command 3­2 Console 3.1 Console Commands Table 3­1 Console Commands Command Description boot Boots the operating system build eeprom Creates a new EEPROM image cdp Performs basic configuration management of DSSI devices clear Clears the specified EEPROM option, removes a boot specification environment variable, or clears the terminal screen continue Resumes processing at the point it was interrupted by Ctrl/P crash Restarts the operating system and generates a memory dump create Creates an environment variable deposit Stores data in a specified location examine Displays contents of a memory location, a register, or a de­ vice help Provides basic information on the console commands when the system is in console mode initialize Initializes the entire system or a specified device or sub­ system repeat Repeats a command; stop by entering Ctrl/C set Records the current system configuration in the EE­ PROM, sets the selected EEPROM option, modifies an en­ vironment variable, or connects to another console or serv­ ice show Displays the last saved configuration, device information for a disk or tape adapter, selected EEPROM information, current state of an environment variable, memory module information, information about network devices, or system power status Console 3­3 Table 3­1 Console Commands (Continued) Table 3­2 Boot Command Options Command Description start Begins execution of an instruction at specified address; does not initialize the system stop Stops a specified processor test Tests a specified device, a subsystem, or the entire system (default) update Copies the contents of the EEPROM or FEPROMs on the boot processor to the EEPROM or FEPROMs on the speci­ fied secondary processor(s) # or ! Introduces a comment Option Meaning ­file Boots from the file ­flags Boot flags that qualify the bootstrap. If omitted, the value of the environment variable boot_flags is used. 3­4 Console Table 3­3 Cdp Command Options Table 3­4 Clear EEPROM Command Options Option Meaning ­a Sets device allocation class, allclass ­i Selects interactive mode; set all parameters ­n Sets device node name, nodename (up to 16 characters) ­o Overrides warning messages ­u Sets device unit number, unitnum ­sa allclass Sets allclass for all DSSI devices in the system to the specified value ­sn Sets nodename to either RFhscn or TFhscn h is the device hose number (03) s is the device slot number (114) c is the device channel number (0, 1) n is the device node ID number (06) ­su unitnum Sets the starting unitnum for the first DSSI device in the system to the specified value. Subsequent DSSI unit numbers are incremented from this base. Option Meaning diag_sdd Removes from EEPROM failure information logged by symptom­directed diagnosis diag_tdd Removes from EEPROM failure information logged by test­directed diagnosis log Removes from EEPROM all failure information (symptom­directed diagnosis, test­directed diagnosis, and operating system) symptom Removes from EEPROM all failure information on op­ erating system Console 3­5 Table 3­5 Create Command Option Table 3­6 Deposit and Examine Command Options Option Meaning ­nv Stores the nonvolatile environment variable in EEPROM Option Meaning ­b Defines data size as a byte ­d Disassembles instruction at current address (examine command only) ­h Defines data size as a hexword ­l Defines data size as a longword; initial default ­o Defines data size as an octaword ­q Defines data size as a quadword ­w Defines data size as a word ­n val Number of consecutive locations to modify ­s val Address increment size. Default is data size. ­u Allows access to console private memory, while dis­ abling virtual address protection checks space: Device name and address space, as follows: Device name: xmi0, ka7aa1, or demna0 gpr Defines the address space as the general register set, R0 through R15. Data size is always a longword. ipr Defines the address space as the internal processor registers (IPRs). Data size is always a longword. psl Defines the address space as the processor status longword (PSL). pmem Defines the address space as physical memory; initial default vmem Defines the address space as virtual memory. All ac­ cess and protection checking occur. 3­6 Console Table 3­7 Set EEPROM Command Options Table 3­8 Set Host Command Options Table 3­9 Show EEPROM Command Options Option Meaning field Records the LARS report number and comment manufactur­ ing Records manufacturing information: module serial number and module part number serial Records system serial number Option Meaning ­bus b DSSI bus on which the node resides ­dup Remote node is a DUP server Option Meaning diag_sdd Displays failure information logged by symptom­ directed diagnosis diag_tdd Displays failure information logged by test­directed diagnosis field Displays LARS number and comment manufactur­ ing Displays manufacturing information: module serial number and module part number serial Displays system serial number symptom Displays failure information logged on operating sys­ tem Console 3­7 Table 3­10 Show Power Command Options Table 3­11 Test Command Options Option Meaning ­h History status · the value of each parameter at the last system shutdown ­s Current status (default) main Power status of the main cabinet (default) right Power status of the expander cabinet to the right of the main cabinet left Power status of the expander cabinet to the left of the main cabinet Option Meaning ­write Selects writes to media as well as reads (read­only is the default). Applicable only to disk testing (ignored other­ wise). ­nowrite "list" Used with ­write to prevent selected devices or groups of devices from being written to. ­omit "list" Specifies device not to test; takes a single device or de­ vice list as a qualifier ­t time Run time in seconds for the test command, following system sizing and configuration; default for system test is 600 seconds (10 minutes). ­q "Quiet" option prevents testing start and stop informa­ tional messages from being displayed on the console ter­ minal. Error messages are always reported. 3­8 Console Table 3­12 Update Command Options Option Meaning ­flash Updates the FEPROMs on the specified secondary proc­ essor ­eeprom Updates the EEPROM on the specified secondary proc­ essor For more information: Console Reference Manual Advanced Troubleshooting Console 3­9 3.2 Environment Variables An environment variable is a name and a value association maintained by the console program. The value associated with an environment variable is an ASCII string (up to 127 characters) or an integer. Certain environment variables are typically modified by the user to tailor the recovery behavior of the system on power­up and after system failures. Volatile environment variables are initialized by a system reset; others are nonvolatile across system failures. Environment variables can be created, modified, displayed, and deleted us­ ing the console create, set, show, and clear commands. A default value is associated with any variable that is stored in EEPROM. This default value is used if the EEPROM is unreadable. Table 3­13 Environment Variables Variable Attribute Function auto_action Nonvola­ tile The action the console will take following an error halt. Values are: restart·Automatically restart. If restart fails, boot the operating system. boot·Automatically boot the operating system halt·Enter console mode (default) baud Nonvola­ tile Sets the console terminal port baud rate. Allowable values are 300, 600, 1200, 2400, 4800, and 9600 (default) bootdef_dev Nonvola­ tile The default device or device list from which booting is attempted when no device name is specified by the boot command. boot_file Nonvola­ tile The default file name used for the primary bootstrap when no file name is specified by the boot command, if appropriate. boot_osflags Nonvola­ tile Additional parameters to be passed to the system during booting if none are specified by the boot command with the ­flags quali­ fier. 3­10 Console Table 3­13 Environment Variables (Continued) Variable Attribute Function boot_reset Nonvola­ tile Resets system and displays self­test re­ sults during booting. Default is on. cpu Volatile Selects the current boot processor cpu_enabled Nonvola­ tile A bitmask indicating which processors are enabled to run (leave console mode). Default is 0xff. cpu_primary Nonvola­ tile A bitmask indicating which processors are enabled to become the next boot processor, following the next reset. De­ fault is 0xff. d_harderr Volatile Determines action taken following a hard error. Values are halt (default) and continue. Applies only when using the test command. d_report Volatile Determines level of information pro­ vided by the diagnostic reports. Values are summary (default) and full. Ap­ plies only when using the test com­ mand. d_softerr Volatile Determines action taken following a soft error. Values are continue (default) and full. Applies only when using the test command. dump_dev Non­ volatile Complete device specification of the de­ vice to which operating system are writ­ ten (if supported by the operating sys­ tem). Default value is null. enable_audit Nonvola­ tile When set to on (default), enables the generation of audit trail messages. When set to off, audit trail messages are suppressed. Console initialization sets this to on. Console 3­11 Table 3­13 Environment Variables (Continued) Variable Attribute Function interleave Nonvola­ tile The memory interleave specification. Val­ ues must be default, none, or an explicit interleave list. Default value is default. language Nonvola­ tile Determines whether system displays mes­ sage numbers or message text in English (default). For more information: Console Reference Manual 3­12 Console 3.3 Device Naming Conventions Device names are used in several console commands. A device name is ex­ pressed in the form ddccuuuu.node.channel.slot.hose. Fields are sepa­ rated by periods. Table 3­14 lists the field definitions. Table 3­14 Device Name Fields Field Size Definition dd 2 Protocol used to access the device: du MSCP disk (CI, SI, DSSI) mu MSCP tape (CI, SI, DSSI) ex XMI Ethernet fx XMI FDDI cc 2 (max) Controller letter (azz) assigned by console, based on the system configuration uuuu 4 (max) Unit number of the device (09999) determined by the I/O channel number and the XMI slot number of the adapter node 3 (max) Node number (0255) of the device on a remote (CI or DSSI) bus. If the remote bus is a CI, this is the CI node number of the HSC; if it is a DSSI, this is the node number of the disk. channel 1 Channel number (01); used only if the adapter is a KFMSA slot 2 (max) XMI slot number (114) of the adapter hose 1 Hose number (03) that connects to the I/O bus For more information: Console Reference Manual Operations Manual Console 3­13 3.4 Command Syntax b[oot] [­fl[ags] ] [­fi[le] ] bu[ild] ee[prom] cdp [­{a,i,n,o,u}] [­sn] [­sa ] [] cl[ear] ee[prom]