digital equipment corporation maynard, massachusetts MS7AA Memory Technical Manual Order Number EKMS7AATM.001 The MS7AA memory module is designed for computer systems built around the LSB bus. The module can be configured in incremental storage capacities ranging from 64 Mbytes to 2 Gbytes. First Printing, November 1992 The information in this document is subject to change without notice and should not be construed as a com­ mitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. The software, if any, described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license. No responsibility is assumed for the use or reliability of soft­ ware or equipment that is not supplied by Digital Equipment Corporation or its affiliated companies. Copyright © 1992 by Digital Equipment Corporation. All Rights Reserved. Printed in U.S.A. The following are trademarks of Digital Equipment Corporation: Alpha AXP DECUS VAXBI AXP DWMVA VAXELN DEC OpenVMS VMScluster DECchip ULTRIX XMI DEC LANcontroller UNIBUS The AXP logo DECnet VAX OSF/1 is a registered trademark of the Open Software Foundation, Inc. FCC NOTICE: The equipment described in this manual generates, uses, and may emit radio frequency en­ ergy. The equipment has been type tested and found to comply with the limits for a Class A computing de­ vice pursuant to Subpart J of Part 15 of FCC Rules, which are designed to provide reasonable protection against such radio frequency interference when operated in a commercial environment. Operation of this equipment in a residential area may cause interference, in which case the user at his own expense may be required to take measures to correct the interference. iii Contents Preface ............................................................................................................................................ vii Chapter 1 Overview 1.1 Major Sections ............................................................................................................... 1­2 1.1.1 Memory Interface Controller ................................................................................. 1­2 1.1.2 Memory Data Controller ........................................................................................ 1­3 1.1.3 DRAM Arrays ......................................................................................................... 1­3 1.2 Internal Buses ............................................................................................................... 1­3 1.3 Transactions .................................................................................................................. 1­3 1.4 Refresh ........................................................................................................................... 1­3 Chapter 2 Memory Interface Controller 2.1 Components ................................................................................................................... 2­1 2.2 Logic Elements .............................................................................................................. 2­1 2.2.1 Command Decode Logic ......................................................................................... 2­2 2.2.2 Address Decode Logic ............................................................................................. 2­2 2.2.2.1 Node Space CSR Transactions ........................................................................ 2­2 2.2.2.2 Memory Space Transactions ............................................................................ 2­3 2.2.3 DRAM Address Logic ............................................................................................. 2­3 2.2.4 DRAM Control Logic .............................................................................................. 2­3 2.2.5 MIC Data Path Logic .............................................................................................. 2­3 2.2.6 Data Wrapping ....................................................................................................... 2­4 2.2.7 Refresh Logic .......................................................................................................... 2­4 2.2.8 Self­Test Logic ........................................................................................................ 2­5 2.2.9 LSB State Machine Control Logic ......................................................................... 2­5 Chapter 3 Memory Data Controller 3.1 MDC Data Paths ........................................................................................................... 3­1 3.2 MDC Transactions ....................................................................................................... 3­1 3.2.1 Read and Wrapped Read Transactions ................................................................ 3­1 3.2.2 Write and Wrapped Write Transactions ............................................................... 3­2 Chapter 4 Memory Organization 4.1 Memory Capacity .......................................................................................................... 4­1 4.2 Memory Banking ........................................................................................................... 4­1 4.3 Memory Interleaving .................................................................................................... 4­2 iv Chapter 5 LSB Memory Signals Chapter 6 Memory Transactions 6.1 Memory Read Transactions .......................................................................................... 6­1 6.1.1 LSB Stalled Read Transactions ............................................................................. 6­1 6.1.2 Module Stalled Read Transactions ........................................................................ 6­1 6.2 Memory Write Transactions ......................................................................................... 6­1 6.2.1 LSB Stalled Write Transactions ............................................................................ 6­2 6.2.2 Module Stalled Write Transactions ....................................................................... 6­2 6.3 Memory Transaction Ordering ..................................................................................... 6­2 6.4 ECC Conversion ............................................................................................................ 6­2 Chapter 7 Registers 7.1 Node Space Base Addresses ......................................................................................... 7­1 7.2 Bit Access Type Acronyms ............................................................................................ 7­2 7.3 Register Descriptions .................................................................................................... 7­3 LDEV·Device Register ........................................................................................ 7­4 LBER·Bus Error Register .................................................................................... 7­5 LCNR· Configuration Register ............................................................................ 7­7 IBR·Information Base Repair Register ............................................................... 7­8 LBESR0­3·Error Syndrome Registers ................................................................ 7­9 LBECR0,1·Error Command Registers .............................................................. 7­10 MCR·Memory Configuration Register .............................................................. 7­12 AMR·Address Mapping Register ....................................................................... 7­14 MSTR0,1·Memory Self­Test Registers .............................................................. 7­17 FADR·Failing Address Register ........................................................................ 7­20 MERA·Memory Error Register A ...................................................................... 7­21 MSYNDA·Memory Error Syndrome Register A ............................................... 7­24 MDRA·Memory Diagnostic Register A ............................................................. 7­25 MCBSA·Memory Check Bit Substitute Register A .......................................... 7­28 MERB·Memory Error Register B ...................................................................... 7­29 MSYNDB·Memory Error Syndrome Register B ............................................... 7­31 MDRB·Memory Diagnostic Register B ............................................................. 7­32 MCBSB·Memory Check Bit Substitute Register B .......................................... 7­34 Chapter 8 Error Conditions 8.1 Memory­Related LSB Errors ........................................................................................ 8­1 8.2 Memory­Specific Errors ................................................................................................ 8­1 8.3 Error Syndrome Decoding ............................................................................................ 8­1 8.3.1 Quadword Memory Error Syndrome Decoding ..................................................... 8­2 8.3.2 Longword Memory Error Syndrome Decoding ..................................................... 8­4 Chapter 9 Self­Test 9.1 Self­Test Report ............................................................................................................ 9­1 9.2 Self­Test Modes ............................................................................................................. 9­1 9.3 Self­Test Performance ................................................................................................... 9­2 v Figures 1­1 Memory Module Block Diagram ................................................................................... 1­2 4­1 Two­Way Interleave of a 128­Mbyte DRAM Array ..................................................... 4­2 4­2 Eight­Way System Interleave of Four 128­Mbyte Memory Modules ......................... 4­3 4­3 Interleaving Different Size Memory Modules ............................................................. 4­4 5­1 LSB D<127:0> During Command/Address Cycles ...................................................... 5­1 5­2 LSB D<127:0> During CSR Data Cycles ..................................................................... 5­2 Tables 1 Definitions of Terms Used in This Document ............................................................... ix 2 DEC 7000/10000 and VAX 7000/10000 Documentation ................................................ x 3 Related Documents ........................................................................................................ xii 2­1 LSB Commands for Memory Operations ..................................................................... 2­2 2­2 LSB Data Wrapping ...................................................................................................... 2­4 2­3 Refresh Rates at Various LSB Cycle Times ................................................................ 2­4 3­1 MDC Wrap Ordering ..................................................................................................... 3­2 4­1 Memory Array Capacity ............................................................................................... 4­1 5­1 LSB Memory Signals .................................................................................................... 5­2 7­1 LSB Node Space Base Addresses ................................................................................. 7­1 7­2 Access Types of Register Bits ....................................................................................... 7­2 7­3 Memory Module Registers ............................................................................................ 7­3 7­4 LDEV Register Bit Definitions ..................................................................................... 7­4 7­5 LBER Register Bit Definitions ..................................................................................... 7­6 7­6 LCNR Register Bit Definitions ..................................................................................... 7­7 7­7 IBR Register Bit Definitions ........................................................................................ 7­8 7­8 LBESR Register Bit Definitions ................................................................................... 7­9 7­9 LBECR Register Bit Definitions ................................................................................ 7­10 7­10 MCR Register Bit Definitions .................................................................................... 7­13 7­11 AMR Register Bit Definitions ..................................................................................... 7­14 7­12 MSTR Register Bit Definitions .................................................................................. 7­17 7­13 Memory Error Address Segments ............................................................................. 7­18 7­14 FADR Register Bit Definitions ................................................................................... 7­20 7­15 MERA Register Bit Definitions .................................................................................. 7­21 7­16 MSYNDA Register Bit Definitions ............................................................................. 7­24 7­17 MDRA Register Bit Definitions .................................................................................. 7­25 7­18 MCBSA Register Bit Definitions ................................................................................ 7­28 7­19 MERB Register Bit Definitions .................................................................................. 7­30 7­20 MSYNDB Register Bit Definitions ............................................................................. 7­31 7­21 MDRB Register Bit Definitions .................................................................................. 7­32 7­22 MCBSB Register Bit Definitions ................................................................................ 7­34 8­1 Quadword Error Syndrome Table ................................................................................ 8­2 8­2 Longword LSB Error Syndrome Table ........................................................................ 8­5 9­1 Memory Self­Test Times ............................................................................................... 9­2 vii Preface Intended Audience This manual describes the bit­level hardware functions of the MS7AA memory module used in computer systems designed around the LSB bus. It is written for developers of system and application software. It assumes machine level programming knowledge and familiarity with the operating system. Document Structure The material is presented in nine chapters. · Chapter 1, Overview, presents an overall introduction to the MS7AA memory module. · Chapter 2, Memory Interface Controller, describes the hardware interface to the LSB bus and discusses the functions of the logic ele­ ments implemented on the MIC chips. · Chapter 3, Memory Data Controller, describes the interface be­ tween the MIC chips and the dynamic random access memory array of the memory module. · Chapter 4, Memory Organization, describes how memory is organ­ ized on a single module or multiple modules and explains how memory performance is enhanced by dividing the DRAMs into two banks and using interleaving techniques. · Chapter 5, LSB Memory Signals, describes the signals used by the memory module to communicate with the LSB bus. · Chapter 6, Memory Transactions, describes how read and write op­ erations are executed on the memory modules. · Chapter 7, Registers, lists the LSB­required and memory­specific reg­ isters and provides bit­level functional descriptions of each register. · Chapter 8, Error Conditions, describes the two categories of errors detected by the memory module and explains how errors are reported in associated error syndrome registers. · Chapter 9, Self­Test, tells when a memory module performs a self­test and gives a brief overview of functions that the memory self­test pro­ vides. viii Conventions Used in This Document Results and Operations Results of operations termed UNPREDICTABLE must not be used by soft­ ware. Operations termed UNDEFINED do not cause the processor to hang, that is, reach a state from which there is no transition to a normal state of in­ struction execution. Nonprivileged software cannot invoke UNDEFINED operations. Register and Bit Designations Certain conventions are followed in register descriptions and in references to bits and bit fields: · Registers are referred to by their mnemonics, such as MCR register. The full name of a register (for example, Memory Configuration Register) is spelled out only at the top of the register description page, or when the register is first introduced. · Bits and fields are enclosed in angle brackets. For example, bit <31> and bits <31:16>. For clarity of reference, bits are usually specified by their numbers or names enclosed in angle brackets adjacent to the register mnemonic, such as AMR<31:17> or AMR, which are equivalent designations. · When the value of a bit position is given explicitly in a register dia­ gram, the information conveyed is as follows: · Fields noted as must be zero (MBZ) must never be filled by software with a nonzero value. · The entry in the type column of a register description table may in­ clude the initialization value of the bits. For example, entry "R/W, 0" indicates a read/write bit that is initialized to 0. Bit Value Designation Meaning 0 1 X Reads as zero; ignored on writes. Reads as one; ignored on writes. Does not exist in hardware. The value of the bit is unpredictable on reads and ignored on writes. ix Terminology Table 1 gives the definition of terms and some mnemonics used in this document. Table 1 Definitions of Terms Used in This Document Term Definition Bank Block DDB LSB MDB MDC MIC String 32­bit ECC 64­bit ECC Smallest group of DRAMs that can be interleaved. A bank consists of one or more strings. 64 bytes of data within naturally aligned boundaries. DRAM data bus. The 576­bit bidirectional data bus that interfaces be­ tween the DRAM chips and the MDC gate arrays. The system bus. Memory data bus. The 144­bit bidirectional data bus is the interface be­ tween the MIC gate arrays and the MDC gate arrays. Memory data controller. Chips that buffer data between the MIC and the DRAM arrays. Memory interface controller. The interface of the memory subsystem to the LSB. The smallest group of DRAMs (144 1/4M x 4) needed to store and retrieve 64 bytes of data per LSB transaction. In some array implementations, the number of banks and strings can be equal, while in others there may be more strings than banks. Synonymous with longword ECC. Synonymous with quadword ECC. x Documentation Titles Table 2 lists the books in the DEC 7000/10000 and VAX 7000/10000 docu­ mentation sets. Table 3 lists other documents that you may find useful. Table 2 DEC 7000/10000 and VAX 7000/10000 Documentation Title 7000 Systems Order Number 10000 Systems Order Number Installation Kit EK7000BDK EK1000BDK Site Preparation Guide EK7000BSP EK1000BSP Installation Guide EK700EBIN EK100EBIN Hardware User Information Kit EK7001BDK EK1001BDK Operations Manual EK7000BOP EK1000BOP Basic Troubleshooting EK7000BTS EK1000BTS Service Information Kit·VAX 7000 EK7002ADK EK1002ADK Platform Service Manual EK7000ASV EK1000ASV System Service Manual EK7002ASV EK1002ASV Pocket Service Guide EK7000APG EK1000APG Advanced Troubleshooting EK7001ATS EK1001ATS Service Information Kit·DEC 7000 EK7002BDK EK1002ADK Platform Service Manual EK7000ASV EK1000ASV System Service Manual EK7002BSV EK1002ASV Pocket Service Guide EK7700APG EK1100APG Advanced Troubleshooting EK7701ATS EK1101ATS Reference Manuals Console Reference Manual EK70C0BTM KA7AA CPU Technical Manual EKKA7AATM KN7AA CPU Technical Manual EKKN7AATM MS7AA Memory Technical Manual EKMS7AATM I/O System Technical Manual EK70I0ATM Platform Technical Manual EK7000ATM xi Table 2 DEC 7000/10000 and VAX 7000/10000 Documentation (Continued) Title 7000 Systems Order Number 10000 Systems Order Number Upgrade Manuals KA7AA CPU Installation Guide EKKA7AAIN KN7AA CPU Installation Guide EKKN7AAIN MS7AA Memory Installation Guide EKMS7AAIN KZMSA Adapter Installation Guide EKKXMSXIN DWLMA XMI PIU Installation Guide EKDWLMAIN DWMBB VAXBI PIU Installation Guide EKDWMBBIN H7237 Battery PIU Installation Guide EKH7237IN H7263 Power Regulator Installation Guide EKH7263IN Futurebus+ PIU Installation Guide EKDWLAAIN BA654 DSSI Disk PIU Installation Guide EKBA654IN BA655 SCSI Disk and Tape PIU Installa­ tion Guide EKBA655IN Removable Media Installation Guide EKTFRRDIN xii Table 3 Related Documents Title Order Number General Site Preparation Site Environmental Preparation Guide EKCSEPGMA System I/O Options BA350 DECstor/me Modular Storage Shelf Subsystem Configuration Guide EKBA350CG BA350 DECstor/me Modular Storage Shelf Subsystem User's Guide EKBA350UG BA350­LA DECstor/me Modular Storage Shelf User's Guide EK350LAUG CIXCD Interface User Guide EKCIXCDUG DEC FDDIcontroller 400 Installation/Problem Solving EKDEMFAIP DEC LANcontroller 400 Installation Guide EKDEMNAIN DEC LANcontroller 400 Technical Manual EKDEMNATM DSSI VAXcluster Installation and Troubleshooting Manual EK410AAMG InfoServer 150 Installation and Owner's Guide EKINFSVOM KDM70 Controller User Guide EKKDM70UG KFMSA Module Installation and User Manual EKKFMSAIM KFMSA Module Service Guide EKKFMSASV RRD42 Disc Drive Owner's Manual EKRRD42OM RF Series Integrated Storage Element User Guide EKRF72DUG TF85 Cartridge Tape Subsystem Owner's Manual EKOTF85OM TLZ06 Cassette Tape Drive Owner's Manual EKTLZ06OM Operating System Manuals Alpha Architecture Reference Manual EYL520EDP DEC OSF/1 Guide to System Administration AAPJU7ATE DECnet for OpenVMS Network Management Utilities AAPQYAATK Guide to Installing DEC OSF/1 AAPS2DATE OpenVMS Alpha Version 1.0 Upgrade and Installation Manual AAPQYSATE VMS Upgrade and Installation Supplement: VAX 7000600 and VAX 10000600 Series AAPRAHATE VMS Network Control Program Manual AALA50ATE xiii Table 3 Related Documents (Continued) Title Order Number VMSclusters and Networking HSC Installation Manual EKHSCMNIN SC008 Star Coupler User's Guide EKSC008UG VAX Volume Shadowing Manual AAPBTVATE Peripherals Installing and Using the VT420 Video Terminal EKVT420UG LA75 Companion Printer Installation and User Guide EKLA75XUG Overview 1­1 Chapter 1 Overview The MS7AA memory module connects directly to the LSB bus and provides up to 2 Gbytes of dynamic random access memory (DRAM) to the CPU. The LSB memory subsystem features the following: · 64­Mbyte to 2­Gbyte memory capacity per module · Incremental configuration to a maximum of seven modules in a single­ processor system · 1­, 2­, 4­, and 8­way interleaving · 64­byte block transfers, 16 bytes at a time, over the system bus · Memory modules with DRAM arrays of 1M x 4 or 4M x 4 components · Bit scattering to provide correction of data if a single DRAM fails · Read and write data wrapping on 32­byte naturally aligned boundaries · Quadword ECC protection that allows detection and correction of single­bit failures and detection of 2­bit failures · Conversion logic that translates quadword ECC (DRAM ECC) to longword ECC (LSB ECC) during memory reads and longword ECC to quadword ECC during memory writes Figure 1­1 shows the architecture of a memory module. 1­2 Overview Figure 1­1 Memory Module Block Diagram 1.1 Major Sections An MS7AA module consists of three major sections: · Memory interface controller (MIC) · Memory data controller (MDC) · DRAM arrays The major sections communicate with each other through internal buses. 1.1.1 Memory Interface Controller The memory interface controller (MIC) is comprised of two gate arrays, MIC­A and MIC­B. It provides the interface to the LSB, controls DRAM timing and refresh, runs memory self­test, and contains all LSB­required and memory­specific registers. The MIC­A interfaces to LSB D<63:0> and the LSB control signals. It de­ codes the LSB command and determines if the memory module is selected for this transaction. The MIC­A provides the address and control signals for the two banks and contains most of the CSRs. The MIC­B interfaces to LSB D<127:64>. It is strictly a data path, with some error checking logic and MIC­B­specific CSRs. The operation of the MIC­B is controlled by the MIC­A. Overview 1­3 1.1.2 Memory Data Controller The memory data controller (MDC) consists of DRAM buffers that reside between the MIC and the DRAM arrays. During a memory write, the MDC buffers accumulate the four LSB data cycles into a 64­byte packet that is written to the DRAMs in a single operation. During a memory read, the DRAM buffers store 64 bytes of data, then parcel it to the MIC, which in turn parcels it out to the LSB in four consecutive 16­byte cycles under the control of the MIC­A. 1.1.3 DRAM Arrays The DRAM arrays consist of DRAMs, control signal, and address buffer components. The MS7AA memory modules can use DRAM sizes of 1M x 4 bits or 4M x 4 bits. The DRAM arrays are organized into 1 to 8 strings. Each string requires 144 DRAMs (using DRAMs with quadword ECC), re­ gardless of the DRAM type. A single string supports 64 Mbytes of memory when configured with 4­Mbit DRAMs, and 256 Mbytes of memory when configured with 16­Mbit DRAMs. The DRAM array on each memory mod­ ule is configured with two independently accessible banks. Interleaving of DRAM banks increases memory bandwith. Each memory module supports 2­way interleaving when configured with a minimum of two strings. Interleaving occurs between the two independently accessible banks within a module. A memory configuration on the LSB consisting of four memory modules, with at least two strings each, supports a maxi­ mum of 8­way interleaving. 1.2 Internal Buses Data within the memory modules is transferred through two internal buses: the memory data bus (MDB) and the DRAM data bus (DDB). The MDB bus transfers data between the MIC chips and the MDC chips. The DDB bus transfers data between the MDC chips and the DRAM arrays. 1.3 Transactions Memory responds to but cannot initiate LSB transactions. It responds to accesses to the memory space and to its own LSB node space. Memory does not respond to any transaction in LSB broadcast space. Memory modules run synchronously with the LSB. Memory transfers con­ sist of four contiguous, 16­byte data cycles, for a total of 64 bytes per trans­ action. Up to three pipelined transactions can be in progress on the LSB bus at a given time. Read and write data wrapping is supported on 32­ byte naturally aligned boundaries. 1.4 Refresh Each memory module implements DRAM refresh. Module refresh is reset and restarted under two different conditions: power­up and system reset. All modules with the same DRAM refresh rate requirements refresh at the same time. Memory Interface Controller 2­1 Chapter 2 Memory Interface Controller The memory interface controller (MIC) controls data movement between the memory DRAM arrays and the LSB bus. 2.1 Components The MIC consists of two 64­bit gate arrays, MIC­A and MIC­B. The MIC­A interfaces to LSB D<63:0>, LSB control/status signals, and LSB ECC<13:0>. It controls the operation of the memory module as well as the operation of the MIC­B. The MIC­A generates the DRAM address and timing functions necessary for all DRAM operations. It also generates all signals used to control the memory data controller (MDC) chips. The MIC­B interfaces to LSB D<127:64> and LSB ECC<27:14>. It func­ tions strictly as a data path consisting of read and write data buffers, ECC logic, and CSRs. The MIC­A implements most of the LSB­required and memory­specific reg­ isters. When a MIC­B control/status register is accessed by the CPU, data is transferred over an 8­bit bidirectional data path connecting the MIC­A and the MIC­B. 2.2 Logic Elements The MIC implements the following logic elements: · Command decode logic · Address decode logic · DRAM address logic · DRAM control logic · MIC data path logic · Data wrapping · Refresh logic · Self­test logic · LSB state machine control logic 2­2 Memory Interface Controller The MIC also contains logic to support the memory data controller (MDC) interface. 2.2.1 Command Decode Logic The LSB command decode logic receives and latches D<37:0> into its ad­ dress latch during LSB command/address cycles. D<37:35> contain the LSB command field. Table 2­1 lists the LSB commands and the associated operations within the memory module. Table 2­1 LSB Commands for Memory Operations 2.2.2 Address Decode Logic Memory responds to two types of transactions: · Node space CSR transactions · Memory space transactions Memory modules do not respond to transactions in LSB broadcast space. 2.2.2.1 Node Space CSR Transactions Node space contains LSB required registers and memory­specific registers accessed on aligned 64­byte boundaries. The MIC decodes the LSB node space address and processes the request to the specified register. All registers are 32 bits wide. Since not all fields within registers contain a valit bit, CSR transactions involving bit fields with no associated valid bits return UNPREDICTABLE data on reads. Writes to nonexistent bits have no effect on module operations. The MIC acknowledges memory node space requests whether the ad­ dressed CSR actually exists or not. Writes to nonexistent CSRs result in UNDEFINED operations. Reads to nonexistent CSRs return UNPRE­ DICTABLE data. D<37:35> Command Memory Operation 000 001 010 011 100 101 110 111 Read Write Reserved Victim Write Read CSR Write CSR Reserved Private Read memory at address specified on LSB D<34:0>. Write memory at address specified on LSB D<34:0>. Ignore command. Write memory at address specified on LSB D<34:0>. Read memory CSR at address specified on LSB D<34:0>. Write memory CSR at address specified on LSB D<34:0>. Ignore command. Ignore command. Memory Interface Controller 2­3 2.2.2.2 Memory Space Transactions The address decode logic compares the LSB address with bits from the Ad­ dress Mapping Register (AMR) to determine if the memory module is se­ lected for the current transaction. Various fields in the AMR register al­ low selection of memory space address decode parameters as described in the discussion of the AMR register in Chapter 7. To support two banks per module, the address decode logic implements two independent address paths. 2.2.3 DRAM Address Logic The DRAM address logic generates row and column address bits for vari­ ous memory configurations from the LSB address. 2.2.4 DRAM Control Logic The timing of DRAM components requires that control signals, along with the row and column addresses, conform to strict parameters. Each memory bank implements a DRAM timing generator to ensure that all DRAM con­ trol signals are properly sequenced during LSB memory access, module re­ fresh, and module self­test. In addition to DRAM control, the two timing generators pass control infor­ mation between each other. Since there is one common data path between the MIC and the MDCs, communication between the two DRAM timing generators is needed to prevent data path conflicts. 2.2.5 MIC Data Path Logic The MIC data path can be broken down into two distinct blocks. The data path to/from the DRAMs and the data path to/from the CSRs. The data path to/from memory consists of a write path and a read path. Within each path there are data buffers and ECC logic. The data path to/from the CSRs implements parity generation logic needed to generate LSB parity on returning CSR read data. The MIC data path logic implements a 4 x 16 byte write buffer and a 4 x 16 byte read buffer that are used as temporary storage elements on the write data path and the read data path, respectively. Storage of LSB write data is necessary when the MDCs are busy with a previous write transaction. Storage of LSB read data is necessary when LSB STALL is asserted by a node other than the memory node supplying the requested read data. The buffers are designed to minimize delays on the data paths. The LSB operates on a 32­bit ECC algorithm, while memory stores and re­ trieves data with a 64­bit ECC algorithm. The write data path logic checks, corrects, and then converts LSB longword (32­bit) ECC into quadword (64­bit) ECC that is stored in each memory module. Similarly, the read data path ECC logic checks, corrects, and then converts quadword (64­bit) ECC used by memory into longword (32­bit) ECC used by the LSB. 2­4 Memory Interface Controller 2.2.6 Data Wrapping The data wrapping logic controls the alignment of data in the MDC chips. LSB supports read and write data wrapping on 32­byte boundaries. During an LSB command/address cycle, LSB D<0> is deasserted on all naturally aligned 64­byte block transactions. It is asserted when the commander node issues the second 32 bytes of data prior to the first 32 bytes on write transactions, and expects the second 32 bytes of data prior to the first 32 bytes on read transactions. Table 2­2 defines the wrapping of read or write data depending upon the state of LSB D<0> latched during a command/address cycle. Table 2­2 LSB Data Wrapping 2.2.7 Refresh Logic The refresh logic refreshes the memory module approximately every 15.6 microseconds regardless of DRAM type (4 Mbit, 16 Mbit). The refresh pe­ riod is generated by a 10­bit divide­by counter from LSB clocks. The actual count value is 780 ticks. A given module can be refreshed at the nominal rate, 2 or 4 times the nominal rate as determined by bits in the Memory Diagnostic Register. Upon power­up or reset, the default refresh rate is the nominal value. Table 2­3 lists the refresh rate at various LSB cycle times. Table 2­3 Refresh Rates at Various LSB Cycle Times Each memory module is refreshed independently of the other memory modules. Both banks of a memory array (all strings) are refreshed simulta­ neously with one exception: when an LSB read or write transaction is cur­ rently being serviced by one of the banks, refresh of the bank may be held off until the transaction has completed. Refresh is performed on the mem­ ory bank immediately following the completion of the transaction. LSB D<0> Data Cycle Ordering 0 1 Octaword­1, Octaword­2, Octaword­3, Octaword­4 Octaword­3, Octaword­4, Octaword­1, Octaword­2 LSB Cycle Time (ns) Refresh Rate 16 17 18 19 20 12.48 13.26 14.04 14.82 15.60 Memory Interface Controller 2­5 2.2.8 Self­Test Logic Upon power­up, system reset, or when EXST_A (bit <4> of the Memory Di­ agnostic Register A) is set by software, each module executes a self­test de­ signed to test and initialize the DRAMs with good ECC. While self­test is executing, any reference to memory space is NO ACKed. CSR space can be accessed during self­test execution. However, writes to the Memory Diag­ nostic Register A (MDRA) and Memory Diagnostic Register B (MDRB) can result in UNPREDICTABLE behavior. See Chapter 9 for self­test times. 2.2.9 LSB State Machine Control Logic The LSB state machine control logic controls the data path interface to/from the LSB and all CSR operations (read/write). This logic also starts the DRAM timing generators. Memory Data Controller 3­1 Chapter 3 Memory Data Controller The memory data controller (MDC) is the data interface between the DRAMs and the memory interface controller (MIC). It connects the 576­bit DRAM data path to the 144­bit MIC data path. The MDC operates under the control of the MIC. 3.1 MDC Data Paths The MDC provides separate read and write data paths to the DRAM array on one side and the MIC on the other. Each MDC block is composed of eighteen MDC chips. Each MDC chip in­ terfaces between a 32­bit bidirectional DDB (DRAM data bus) port and an 8­bit bidirectional MDB (MIC data bus) port. Both ports are controlled by the MIC­A. 3.2 MDC Transactions MDC supports four types of transactions: · Read · Wrapped read · Write · Wrapped write 3.2.1 Read and Wrapped Read Transactions During a read transaction, the MDC chip receives DRAM read data on the DDB<31:0> port and loads it in its internal read data buffer. Once four bytes of data are assembled in the read data buffer, the MDC chip drives the content of the read data buffer onto the MDB<7:0> port in four sepa­ rate clock cycles. When data wrapping is selected, the order in which read data is trans­ ferred to the MIC is altered, as shown in Table 3­1. 3­2 Memory Data Controller Table 3­1 MDC Wrap Ordering 3.2.2 Write and Wrapped Write Transactions During a write transaction, the MDC chip receives DRAM write data on the MDB<7:0> port and loads it in its internal write data buffer in four consecutive cycles. Once the data is assembled in the write data buffer, the MDC drives the contents of the write data buffer onto the DDB<31:0> port. When data wrapping is selected, the order in which write data is latched into the MDC is altered (see Table 3­1) so that data written to the DRAMs is not wrapped. Cycle No. Octaword No. Wrap Disabled (LSB D<0>=0) Octaword No. Wrap Enabled (LSB D<0>=1) 1 2 3 4 1 2 3 4 3 4 1 2 Memory Organization 4­1 Chapter 4 Memory Organization The system supports up to seven memory modules in single­processor configurations. The physical memory composed of a single or multiple memory modules can be organized in various ways to optimize memory access. 4.1 Memory Capacity Memory can be configured with MS7AA modules of various capacities, from 64 Mbytes to 2 Gbytes. The DRAM arrays consist of DRAMs, con­ trol signals, and address buffer components. The memory modules can use DRAM sizes of 4 Mbits or 16 Mbits. The DRAM arrays are organized into 1 to 8 strings. Each string requires 144 DRAMs (using 1M x 4 or 4M x 4 DRAMs). A single string supports 64 Mbytes of memory when con­ figured with 4­Mbit DRAMs, and 256 Mbytes of memory when configured with 16­Mbit DRAMs. Table 1­1 lists array capacities that can be config­ ured based upon the number of strings on a module and the DRAM type. Table 4­1 Memory Array Capacity 4.2 Memory Banking DRAM arrays on all memory modules containing more than one string are organized as two banks, Bank 0 and Bank 1. A bank is a grouping of one or more strings that share a common address path. Each bank has its own set of control, address, and timing signals and is accessible inde­ DRAM Type (Mbits) Number of Strings Memory Capacity (Mbytes) 4 4 4 4 16 16 16 16 1 2 4 8 1 2 4 8 64 128 256 512 256 512 1024 2048 4­2 Memory Organization pendently. This arrangement prevents memory idling by allowing access to the second bank while the first bank is still busy. 4.3 Memory Interleaving Further enhancement of memory performance can be achieved by inter­ leaving the physical memory. Interleaving can be done at two levels: mod­ ule and system. At the module level, the DRAM arrays can be interleaved on 64­byte block boundaries. Each memory module supports 2­way interleaving when con­ figured with a minimum of two strings. Interleaving occurs between the two independently accessible banks within a module. Figure 4­1 shows a 2­way interleaved 2­string memory module. The DRAM array in a 2­ string MS7AA memory module is always interleaved. Figure 4­1 Two­Way Interleave of a 128­Mbyte DRAM Array In multi­module memory subsystems, three modes of interleave are possi­ ble at the system level: default, explicit, and none. The interleave mode selection parameters are stored in the console EEPROM and can be modi­ fied through the console program. Initialization software uses registers in LSB commanders and each memory module to configure the memory inter­ leave as specified by the EEPROM parameters. A memory configuration consisting of four memory modules supports a maximum of 8­way inter­ leaving when each of the four modules is 2­way interleaved. The three ad­ ditional modules (modules 5 to 7), if present, can be configured into the system as two modules 4­way interleaved and 1 module 2­way interleaved. Figure 4­2 shows four memory modules in an 8­way interleaved organiza­ tion. Memory Organization 4­3 Figure 4­2 Eight­Way System Interleave of Four 128­Mbyte Memory Modules If the EEPROM specifies default interleave, the console attempts to form interleave sets so that the largest interleave factor is obtained for each group of DRAM arrays. The default mode optimizes interleaving of memory in any arrangement of memory modules. For example, two 128­Mbyte modules can be combined to appear as a single 256­Mbyte module that can then be interleaved with a single 256­Mbyte module. In this configuration, three modules are 2­ way interleaved among each other. This type of configuration yields 2­way module interleaving and 4­way system­level interleaving as shown in Fig­ ure 4­3. 4­4 Memory Organization Figure 4­3 Interleaving Different Size Memory Modules If the EEPROM specifies explicit interleave sets, the console then inter­ leaves the arrays as requested. In a noninterleave mode, the console con­ figures arrays in order, by node number, with the lowest numbered array at the lowest physical address. LSB Memory Signals 5­1 Chapter 5 LSB Memory Signals A memory module interfaces the LSB bus through a total of 173 signals. This chapter lists the LSB memory signals and describes their functions. Refer to the Platform Technical Manual for a complete listing of the LSB bus signals. Table 5­1 lists the LSB memory signals and identifies their functions. LSB Data D<127:0> The LSB data signals transfer command/address and data information be­ tween nodes. A memory module receives command/address cycles. It drives and receives data cycles. During command/address cycles, only D<38:0> contain valid information (see Figure 5­1). D<38> carries the parity bit protecting the command and address information in D<37:0>. D<127:39> contain UNDEFINED data that will be ignored. Figure 5­1 LSB D<127:0> During Command/Address Cycles During CSR data cycles, D<31:0> transfer the CSR data. D<37:32> contain UNDEFINED data (see Figure 5­2). D<38> carries the parity bit for read and write data. A memory module checks for correct parity on CSR writes and supplies correct parity on CSR reads. NOTE: Data is ignored in D<37:32>. However, memory computes CSR data cycle parity over D<37:0>. Hence, for parity checking, D<37:32> are valid. 5­2 LSB Memory Signals Figure 5­2 LSB D<127:0> During CSR Data Cycles Table 5­1 LSB Memory Signals Signal No. of Lines Function CA CNF D<127:0> DIRTY ECC<27:0> ERR NID<2:0> PH0 (SINE) REQ<9:0> RESET STALL 1 1 128 1 28 1 3 1 10 1 1 Command/Address. Asserted by a bus commander to signify a command/address cycle. Confirmation. Asserted by the selected memory module to signify acceptance of a command/address cycle. Data. Command/address and data lines.1 Dirty. Asserted by a CPU module to indicate that the targeted cache block has been modified more recently than the copy in mem­ ory. When asserted during a read transaction, the selected memory module aborts the transaction and does not return read data to the LSB bus. Error Checking and Correction. Error correction lines for data cycles. Error. Asserted when a memory module detects certain LSB and memory­related errors. Node ID. Hardwired lines that indicate the node ID (slot number) of the memory module. Sine. Used to generate the eight copies of the digital clock for each module. Arbitration Request. Asserted by the I/O module or CPU mod­ ules to arbitrate for the LSB bus. Memory modules never assert REQ<9:0>. Reset. Causes a system reset when asserted by a node. Stall. Asserted when the module is unable to accept write data or supply read data. 1 Only D<38:0> are valid during command/address cycles and LSB CSR data cycles. LSB Memory Signals 5­3 LSB CA CA is asserted by an LSB commander node when it is driving a com­ mand/address cycle on the LSB. The memory module receives but never drives this signal. LSB CNF CNF is asserted by memory to confirm the acceptance of a com­ mand/address cycle to either memory or node space. The selected module asserts CNF only when the LSB address matches the module's memory or node space, and no parity errors are detected. LSB D<127:0> Command/address and data lines. LSB DIRTY Memory modules monitor LSB DIRTY. If asserted during an LSB read transaction, memory does not supply read data for the transaction associ­ ated with the assertion of LSB DIRTY. The node that asserted DIRTY supplies the read data in place of memory. LSB ECC Signals ECC<27:0> LSB ECC signals carry the longword ECC check bits protecting D<127:0> during memory space read or write data cycles. During the four memory space write data cycles, the selected memory mod­ ule receives ECC<27:0>, with write data in D<127:0>, checks and corrects ECC errors before data is written to memory. During read data cycles from memory, a module checks and corrects single­bit ECC errors before data is driven onto LSB. During CSR data cycles, ECC<27:0> contain UNDEFINED data that is ig­ nored. LSB ERR Memory modules monitor and assert ERR under conditions discussed in the Platform Technical Manual. In addition, memory asserts ERR for memory­specific error conditions. Refer to Chapter 8 for additional details. LSB NID<2:0> These three signals indicate the node ID. They are hardwired into the backplane. LSB PH0 (SINE) This is the LSB­supplied clock signal. Each memory module receives and generates multiple copies of a single­phase clock. 5­4 LSB Memory Signals LSB REQ<9:0> Memory modules monitor REQ<9:0> to determine when a command/ ad­ dress cycle will be driven on the LSB. The OR of these ten signals initiates the LSB state machines and gates the address lines to the DRAMs to help reduce power consumption. The decoded DRAM ROW address is sent to all modules and all strings independent of module selection. This is done to speed access time. If a module is not selected for the transaction, or if the bus goes to the idle state, the address drivers are held in their previous state to conserve power. LSB RESET All modules monitor LSB RESET. When asserted, the module is reset to its default power­up state. The assertion of LSB RESET inhibits DRAM re­ fresh. When LSB RESET is deasserted, all memory modules start refresh operation within a specified number of cycles. LSB STALL Memory modules monitor and assert STALL. Memory monitors STALL to ensure that it stays in sync with the bus protocol. Memory asserts STALL for two conditions: · A module asserts STALL when it is not able to supply read data to an LSB commander at the required time due to a memory timing conflict. STALL remains asserted until the conflict is resolved and read data can be driven on the LSB. This condition occurs when a read transac­ tion immediately follows a write transaction on the LSB to the same memory bank. In this instance nine STALLs are asserted on the LSB. · A module asserts STALL when it cannot supply read data or accept write data due to DRAM refresh cycles. In this case 1 to 14 STALLs are asserted on the LSB. Memory Transactions 6­1 Chapter 6 Memory Transactions The design of the memory module architecture ensures that the com­ mand/address issued to the DRAMs is always driven on the address lines of an idle memory bank. This speeds DRAM access during reads. 6.1 Memory Read Transactions During a memory read transaction, DRAM read data is driven onto the MDB bus to both MIC­A and MIC­B in four consecutive clock cycles. The memory module starts the DRAM access 1.5 cycles after a command/ address cycle. A read transaction can be stalled by the LSB bus or by the memory mod­ ule. 6.1.1 LSB Stalled Read Transactions The assertion of LSB STALL by another LSB node during memory read transactions causes the memory module to delay the release of read data to the LSB bus. The DRAM read timing is not affected by the assertion of LSB STALL. Under a stall condition, the DRAM read data is latched either in the MDC chips or is transferred to the read data buffer of the MIC. The DRAM read data remains in the MIC until LSB STALL is deasserted. Read data is driven on the LSB bus two cycles after the deassertion of LSB STALL. 6.1.2 Module Stalled Read Transactions The start of the DRAM access for a memory read transaction may be de­ layed due to conflicts on the memory module. These conflicts result from either DRAM refresh cycles or from DRAM write and read timing. 6.2 Memory Write Transactions During a memory write transaction, LSB write data is latched into the MIC. Data is then transferred from the MIC to the MDC chips through the 144­bit MDB bus in four consecutive cycles. The memory module starts DRAM access a minimum of 12 bus cycles after the com­ mand/address cycle coincident with receiving the write data. A write transaction can be stalled by the LSB bus or by the memory mod­ ule. 6­2 Memory Transactions 6.2.1 LSB Stalled Write Transactions The assertion of LSB STALL by another node delays the start of the DRAM write access until after the first LSB write data has been received. Once the DRAM write has started, it is completed in four consecutive LSB cycles. 6.2.2 Module Stalled Write Transactions The memory module asserts LSB STALL to suppress the generation of write transactions to memory when conflicts on the memory module delay loading of write data into the DRAMs. The stall occurs on the third back­ to­back write transaction to a single module preceded by a DRAM refresh. The memory module maintains LSB STALL assertion until the completion of the refresh cycle. When refresh has completed, the memory module deasserts LSB STALL, and the DRAM cycle for the write transaction starts. 6.3 Memory Transaction Ordering In general, memory transactions are performed on a first come first served protocol. However, this protocol is overruled when a memory read follows a write transaction and targets different banks of the same memory mod­ ule. In this case, the memory read transaction is always performed first to enhance system performance. 6.4 ECC Conversion Memory modules convert LSB longword (32­bit) ECC into quadword (64­ bit) ECC that is stored with LSB data on writes. During LSB reads, quadword ECC is converted to longword ECC as required by the LSB. Quadword ECC requires fewer DRAMs per string. Registers 7­1 Chapter 7 Registers The MS7AA memory module has two groups of registers: · LSB required registers · Module­specific registers LSB required registers are used for internode communication over the LSB bus. Memory­specific registers are used to perform functions unique to the memory module. 7.1 Node Space Base Addresses All memory registers reside on the memory controller interface. They are mapped to the node space as offsets to a base address (BB). The base ad­ dress is implemented in hardware and depends on the node ID of the mod­ ule, which is determined by the LSB slot occupied by the module. Table 7­1 gives the physical base addresses of nodes on the LSB bus for proces­ sors that support a 32­bit address range (for example, KA7AA) and a 34­bit address range (for example, KN7AA). Table 7­1 LSB Node Space Base Addresses Node ID (Slot) Module Physical Base Address (BB) (Byte) 32­Bit Range 34­Bit Range 0 1 2 3 4 5 6 7 8 CPU/Memory CPU/Memory CPU/Memory CPU/Memory CPU/Memory CPU/Memory CPU/Memory CPU/Memory I/O F800 0000 3 F800 0000 F840 0000 3 F840 0000 F880 0000 3 F880 0000 F8C0 0000 3 F8C0 0000 F900 0000 3 F900 0000 F940 0000 3 F940 0000 F980 0000 3 F980 0000 F9C0 0000 3 F9C0 0000 FA00 0000 3 FA00 0000 7­2 Registers 7.2 Bit Access Type Acronyms Acronyms are used throughout register descriptions to indicate the access type of the bit(s). Table 7­2 lists those acronyms. Table 7­2 Access Types of Register Bits Acronym Access Type RO R0 R/W W1C W1S WO Read only; writes ignored. Read as zero. Read/write. Read/write one to clear; unaltered by a write of zero. Write one to set; self­cleared; cannot be cleared by a write of zero. Write only. Registers 7­3 7.3 Register Descriptions Table 7­3 lists the memory module registers and gives the address of each register as an offset from a selected node space base address. Functional descriptions of the memory registers follow. Table 7­3 Memory Module Registers Register Name Mnemonic Address (Byte Offset) LSB Required Device Register Bus Error Register Configuration Register Information Base Repair Register Error Syndrome Register 0 Error Syndrome Register 1 Error Syndrome Register 2 Error Syndrome Register 3 Error Command Register 0 Error Command Register 1 Memory­Specific Memory Configuration Register Address MappingRegister Memory Self­Test Register 0 Memory Self­Test Register 1 Failing Address Register Memory Error Register A Memory Error Syndrome Register A Memory Diagnostic Register A Memory Check Bit Substitute Register A Memory Error Register B Memory Error Syndrome Register B Memory Diagnostic Register B Memory Check Bit Substitute Register B LDEV LBER LCNR IBR LBESR0 LBESR1 LBESR2 LBESR3 LBECR0 LBECR1 MCR AMR MSTR0 MSTR1 FADR MERA MSYNDA MDRA MCBSA MERB MSYNDB MDRB MCBSB BB1 + 0000 BB + 0040 BB + 0080 BB + 00C0 BB + 0600 BB + 0640 BB + 0680 BB + 06C0 BB + 0700 BB + 0740 BB + 2000 BB + 2040 BB + 2080 BB + 20C0 BB + 2100 BB + 2140 BB + 2180 BB + 21C0 BB + 2200 BB + 4140 BB + 4180 BB + 41C0 BB + 4200 1 BB is the node space base address of the memory module in hex. 7­4 Registers LDEV·Device Register Table 7­4 LDEV Register Bit Definitions Address Access BB + 0000 R/W The LDEV register is loaded during initialization with information that identifies a node. Name Bit(s) Type Function DREV <31:16> R/W Device Revision. Identifies the functional revision level of the module. The value of this field is contained in the EEPROM of the memory module and is loaded into the LDEV register by console software at system initialization. For the MS7AA memory module, the value of this field is zero. DTYPE <15:0> R/W Device Type. Loaded at initialization with a value of 4000 (hex), which identifies the node as a memory module. The device type may be modified by console software when the device type field is fetched from the serial EEPROM lo­ cated on the memory module. Registers 7­5 LBER·Bus Error Register Address Access BB + 0040 R/W The LBER register stores the error bits that are flagged in memory operations and logs the failing commander ID. The status of this register remains locked until software resets the error bit(s). 7­6 Registers Table 7­5 LBER Register Bit Definitions Name Bit(s) Type Function RSVD NSES CTCE DTCE DIE SHE CAE NXAE CNFE STE TDE CDPE2 CDPE CPE2 CPE CE2 CE UCE2 UCE E <31:19> <18> <17> <16> <15> <14> <13> <12> <11> <10> <9> <8> <7> <6> <5> <4> <3> <2> <1> <0> R/W, 0 RO, 0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 Reserved. Node­Specific Error Summary. Set when one of bits <11>, <10>, <9>, <5>, or <4> of the MERA regis­ ter is set. Control Transmit Check Error. Not imple­ mented on memory. Data Transmit Check Error. Not implemented on memory. DIRTY Error. SHARED Error. Not implemented on memory. Command/Address Error. Nonexistent Address Error. Not implemented on memory. CNF Error. STALL Error. Transmitter During Error. Second CSR Data Parity Error. Not imple­ mented on memory. CSR Data Parity Error. Not implemented on memory. Second Command Parity Error. Command Parity Error. Second Correctable Data Error. Correctable Data Error. Second Uncorrectable Data Error. Uncorrectable Data Error. Error. Signals assertion of error line. Registers 7­7 LCNR· Configuration Register Table 7­6 LCNR Register Bit Definitions Address Access BB + 0080 R/W The LCNR register contains LSB systemwide configuration setup and status information. Name Bit(s) Type Function STF NRST NHALT RSTSTAT RSVD CEEN <31> <30> <29> <28> <27:1> <0> R/W, 1 WO, 0 R0 R0 R0 R/W, 0 Self­Test Fail. When set, indicates that this node has not yet completed self­test. Memory clears this bit at the completion of self­test regardless of defective loca­ tions found in the DRAM array. Node Reset. When set, the node enters console mode and undergoes a reset sequence. CSRs are reset to their initialized state. Any pending transactions are lost or left uncompleted. Memory self­test halts, if running, and does not restart. An internally generated reset sig­ nal remains asserted for 16 LSB bus cycles after NRST is set, providing sufficient time to reset memory state and clear NRST. If NRST is set, a value of zero must be written to the MDRA register; otherwise, the memory operation is UNDEFINED. Node Halt. Not implemented on memory. Reset Status. Not implemented on memory. Reserved. Read as zero. Correctable Error Detection Enable. When set, enables detection of correctable errors. 7­8 Registers IBR·Information Base Repair Register Table 7­7 IBR Register Bit Definitions Address Access BB + 00C0 R/W The IBR register is used to access the EEPROM on the LSB mem­ ory and I/O modules. The EEPROM access is accomplished through continual updates of this register by software. Name Bit(s) Type Function MBZ SCLK XMT_SDAT RCV_SDAT <31:3> <2> <1> <0> R/W, 0 R/W, 0 R/W, 1 RO, 1 Must Be Zero. Must always be written as zero. Serial Clock. Used by software to implement the EEPROM serial clock interface. When this bit is writ­ ten with a one, the EEPROM serial clock input is forced to logic high. When it is cleared, the serial clock input is forced to logic low. Transmit Serial Data. Used by software to assert the serial data line of the EEPROM to either high or low logic levels. This bit is used with SCLK to transfer com­ mand/address and write data to the EEPROM. Receive Serial Data. Returns the status of the EEPROM serial data line. Used by software to receive serial read data and EEPROM responses. XMT_SDAT must be one to receive an EEPROM response or serial read data. Registers 7­9 LBESR0­3·Error Syndrome Registers Table 7­8 LBESR Register Bit Definitions Address Access BB + 0600 to 06C0 RO The LBESR registers contain the syndrome computed from data received on the LSB D and ECC fields during the cycle when an er­ ror was detected. These registers are locked upon the first ECC detected error and remain locked until all LSB ECC error bits in LBER are cleared. Name Bit(s) Type Function RSVD SYND_0 SYND_1 SYND_2 SYND_3 <31:7> <6:0> <6:0> <6:0> <6:0> R0 RO, 0 RO, 0 RO, 0 RO, 0 Reserved. Read as zero. Syndrome 0. Syndrome computed from D<31:0> and ECC<6:0> during error cycle. Syndrome 1. Syndrome computed from D<63:32> and ECC<13:7> during error cycle. Syndrome 2. Syndrome computed from D<95:33> and ECC<20:14> during error cycle. Syndrome 3. Syndrome computed from D<127:96> and ECC<27:21> during error cycle. 7­10 Registers LBECR0,1·Error Command Registers Table 7­9 LBECR Register Bit Definitions Address Access BB + 0700 and BB + 0740 RO The LBECR registers hold the contents of the LSB command and address fields for the operation during which an error was de­ tected. Name Bit(s) Type Function CA RSVD DCYCLE <31:0> <31:20> <19:18> RO R0 RO Command/Address. Contents of D<31:0> during com­ mand cycle. Reserved. Read as zero. Data Cycle. Value indicates which data cycle had the data error. LBECR<19:18> Data Cycle in Error 00 01 10 11 1 2 3 4 Registers 7­11 Table 7­9 LBECR Register Bit Definitions (Continued) Name Bit(s) Type Function DIRTY SHARED CNF RSVD CID P CMD CA <17> <16> <15> <14:11> <10:7> <6> <5:3> <2:0> RO RO RO R0 R0 RO RO RO Dirty. Set when DIRTY is asserted for the current com­ mand. Shared. Set when SHARED is asserted for the current command. Confirmation. Set when CNF is asserted for the cur­ rent command. Reserved. Read as zero. Commander ID. Reflects the contents of REQ<3:0> dur­ ing a command cycle. Parity. Contents of D<38> during command cycle. Command. Contents of D<37:35> during command cycle. CMD is decoded as follows: Command/ Address. Contents of D<34:32> during com­ mand cycle. Command Function DAS Value1 000 001 010 011 100 101 110 111 Read Write Reserved Write Victim Read CSR Write CSR Reserved Private 00 08 18 20 28 38 1 The hex value commonly found in the low byte of this register when less than 8 Gbytes of memory are present in the system. 7­12 Registers MCR·Memory Configuration Register Address Access BB + 2000 R/W The MCR register provides information about the DRAM array. It is accessed by console software to determine module capacity, that is, the DRAM type (4­Mbit or 16­Mbit) and number of strings in­ stalled. This information is necessary to set up the eight AMR reg­ isters in each LSB commander node and the AMR register located on each memory module at BB+2040. Registers 7­13 Table 7­10 MCR Register Bit Definitions Name Bit(s) Type Function RSVD STRG RSVD DTYP <31:4> <3:2> <1> <0> R0 RO, X R0 RO, X Reserved. Read as zero. String. Supplies information about the number of strings installed on a module. This field, in conjunc­ tion with DTYP, indicates module capacity. It is loaded at system initialization. Reserved. Reads as zero. Device Type. Supplies information about the size of DRAM technology used for the memory module. This bit, along with STRG, indicates module capacity. It is loaded at system initialization. MCR<3:2> No. of Strings 00 01 10 11 1 2 4 8 MCR<0> DRAM Type 0 1 4 Mbit 16 Mbit 7­14 Registers AMR·Address Mapping Register Table 7­11 AMR Register Bit Definitions Address Access BB + 2040 R/W The AMR register is used with the LSB memory address issued during a command/address cycle to select a memory module, a bank within a module, and adjust the address on memory modules based upon the interleave level selected, the number of strings, and the DRAM type. This register is a single copy of the eight mapping registers that CPU modules and the IOP module must implement. When the con­ sole in the primary CPU configures memory, it determines the slots occupied by the memory modules and loads the slot number of each memory module in the AMR register of the module. Copies of the AMR registers are written into the corresponding mapping registers on all CPU nodes and the IOP node. The AMR contents for nodes 0 to 7 are placed into LMMR0­7 registers. If a module is not present in a memory slot, the console writes a zero to bit <0> (Enable) of the corresponding LMMR register. Name Bit(s) Type Function MADR RSVD <31:17> <16:11> R/W, 0 R0 Module Address. The contents of MADR is com­ pared with the LSB address contained on D<34:20> for a match. (MADR bit <17> correlates to LSB ad­ dress line D<20>, and so on.) Reserved. Read as zero. Registers 7­15 Table 7­11 AMR Register Bit Definitions (Continued) Name Bit(s) Type Function NBANKS AW <10:9> <8:5> R/W, 0 R/W, 0 Number of Banks. Specifies the number of banks (1, 2, 4, or 8) contained on individual memory mod­ ules. Address Width. Specifies the number of bits in the LSB address field <34:20> that are significant. Only those bits are compared with the same number of corrersponding bits in the AMR (bits <31:17>). The remaining bits are ignored. The theoretical range of significant bits selected by dif­ ferent values of the AMR is given below. In the initialized state, no bits of D<34:20> are matched to bits AMR<31:17> (AW = 0000). When AW contains a value of 0001, only the MSBs are compared (AMR<31> is compared to LSB<34>). Ac­ cess is allowed if a match occurs. If a value of F (hex) is written in AW, all bits are significant, and the LSB <34:20> must match AMR<31:17>. AMR<10:9> No. of Banks 00 01 10 11 1 2 Reserved Reserved AMR<8:5> Significant Bits Compared LSB Data AMR 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 <34:20> <31:17> <34:21> <31:18> <34:22> <31:19> <34:23> <31:20> <34:24> <31:21> <34:25> <31:22> <34:26> <31:23> <34:27> <31:24> <34:28> <31:25> <34:29> <31:26> <34:30> <31:27> <34:31> <31:28> <34:32> <31:29> <34:33> <31:30> <34> <31> No compare 7­16 Registers Table 7­11 AMR Register Bit Definitions (Continued) Name Bit(s) Type Function IA INTL E <4:3> <2:1> <0> R/W, 0 R/W, 0 R/W, 0 Interleave Address. Determines module selection based upon level of interleave with other memory modules. Interleave. Determines the level of interleave of this module with other modules for a given address space. Enable. Enables the module to respond to LSB memory space transactions. AMR <2:1> Interleave Level 00 01 10 11 1­way interleave. Module is not inter­ leaved with any other module. 2­way interleave. Module is inter­ leaved with one other module. 4­way interleave. Module is inter­ leaved with three other modules. Reserved. Registers 7­17 MSTR0,1·Memory Self­Test Registers Table 7­12 MSTR Register Bit Definitions Table 7­13 gives a listing of memory address segments associated with each bit in the MSTR registers. Address segments are given for 4­Mbit and 16­Mbit DRAM arrays. Address Access BB + 2080 and BB + 20C0 R/W The MSTR registers are used to isolate self­test failures to a given address segment or segments (if multiple failures) within a mod­ ule. The two registers combined break up a memory module into 64 distinct address segments. Each segment resides in a range of ad­ dresses that are sized according to the selected DRAM component (4 Mbits or 16 Mbits). Name Bit(s) Type Function STFAS <31:0> RO, 0 Self­Test Failing Address Segment. A bit in the MSTR registers is set when the associated memory segment fails self­test (is defective) in a noninter­ leaved memory configuration. Each module executes self­test as if it were the only memory module in the system. 7­18 Registers Table 7­13 Memory Error Address Segments Failing Bit MSTR0 4­Mbit 16­Mbit MSTR1 4­Mbit 16­Mbit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0000 to 0000 0000 to 007F FFFF 01FF FFFF 0080 0000 to 0200 0000 to 00FF FFFF 03FF FFFF 0100 0000 to 0400 0000 to 017F FFFF 05FF FFFF 0180 0000 to 0600 0000 to 01FF FFFF 07FF FFFF 0200 0000 to 0800 0000 to 027F FFFF 09FF FFFF 0280 0000 to 0A00 0000 to 02FF FFFF 0BFF FFFF 0300 0000 to 0C00 0000 to 037FFFFF 0DFF FFFF 0380 0000 to 0E00 0000 to 08FF FFFF 0FFF FFFF 0400 0000 to 1000 0000 to 047F FFFF 13FF FFFF 0480 0000 to 1200 0000 to 04FF FFFF 15FF FFFF 0500 0000 to 1400 0000 to 057F FFFF 15FF FFFF 0580 0000 to 1600 0000 to 05FF FFFF 17FF FFFF 0600 0000 to 1800 0000 to 067F FFFF 19FF FFFF 0680 0000 to 1A00 0000 to 06FF FFFF 1BFF FFFF 0700 0000 to 1C00 0000 to 077F FFFF 1DFF FFFF 0780 0000 to 1E00 0000 to 07FF FFFF 1FFF FFFF 1000 0000 to 4000 0000 to 107F FFFF 41FF FFFF 1080 0000 to 4200 0000 to 10FF FFFF 43FF FFFF 1100 0000 to 4400 0000 to 117F FFFF 45FF FFFF 1800 0000 to 4600 0000 to 11FF FFFF 47FF FFFF 1200 0000 to 4800 0000 to 127F FFFF 49FF FFFF 1280 0000 to 4A00 0000 to 12FF FFFF 4BFF FFFF 1300 0000 to 4C00 0000 to 137F FFFF 4DFF FFFF 1380 0000 to 4E00 0000 to 13FF FFFF 4FFF FFFF 1400 0000 to 5000 0000 to 147F FFFF 51FF FFFF 1480 0000 to 5200 0000 to 14FF FFFF 53FF FFFF 1500 0000 to 5400 0000 to 157F FFFF 55FF FFFF 1580 0000 to 5600 0000 to 15FF FFFF 57FF FFFF 1600 0000 to 5880 0000 to 167F FFFF 59FF FFFF 1680 0000 to 5A00 0000 to 16FF FFFF 5BFF FFFF 1700 0000 to 5C00 0000 to 177F FFFF 5FFF FFFF 1780 0000 to 5E00 0000 to 17FF FFFF 5FFF FFFF Registers 7­19 Table 7­13 Memory Error Address Segments (Continued) Failing Bit MSTR0 4­Mbit 16­Mbit MSTR1 4­Mbit 16­Mbit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0800 0000 to 2000 0000 to 087F FFFF 21FF FFFF 0880 0000 to 2200 0000 to 08FF FFFF 23FF FFFF 0900 0000 to 2400 0000 to 097F FFFF 25FF FFFF 0980 0000 to 2600 0000 to 09FF FFFF 27FF FFFF 0A00 0000 to 2800 0000 to 0A7F FFFF 29FF FFFF 0A80 0000 to 2A00 0000 to 0AFF FFFF 2BFF FFFF 0B00 0000 to 2C00 0000 to 0B7F FFFF 2DFF FFFF 0B80 0000 to 2E00 0000 to 0BFF FFFF 2FFF FFFF 0C00 0000 to 3000 0000 to 0C7F FFFF 31FF FFFF 0C80 0000 to 3200 0000 to 0CFF FFFF 33FF FFFF 0D00 0000 to 3400 0000 to 0D7F FFFF 35FF FFFF 0D80 0000 to 3600 0000 to 0DFF FFFF 37FF FFFF 0E00 0000 to 3800 0000 to 0E7F FFFF 39FF FFFF 0E80 0000 to 3A00 0000 to 0EFF FFFF 3BFF FFFF 0F00 0000 to 3C00 0000 to 0F7F FFFF 3DFF FFFF 0F80 0000 to 3E00 0000 to 0FFF FFFF 3FFF FFFF 1800 0000 to 6000 0000 to 187F FFFF 61FF FFFF 1880 0000 to 6200 0000 to 18FF FFFF 63FF FFFF 1900 0000 to 6400 0000 to 197F FFFF 65FF FFFF 1980 0000 to 6600 0000 to 19FF FFFF 67FF FFFF 1A00 0000 to 6800 0000 to 1A7F FFFF 69FF FFFF 1A80 0000 to 6A00 0000 to 1AFF FFFF 6BFF FFFF 1B00 0000 to 6C00 0000 to 1B7F FFFF 6DFF FFFF 1B80 0000 to 6E00 0000 to 1BFF FFFF 6FFF FFFF 1C00 0000 to 7000 0000 to 1C7F FFFF 71FF FFFF 1C80 0000 to 7200 0000 to 1CFF FFFF 73FF FFFF 1D00 0000 to 7400 0000 to 1D7F FFFF 75FF FFFF 1D80 0000 to 7600 0000 to 1DFF FFFF 77FF FFFF 1E00 0000 to 7800 0000 to 1E7F FFFF 79FF FFFF 1E80 0000 to 7A80 0000 to 1EFF FFFF 7BFF FFFF 1F00 to 7C00 0000 to 1F7F FFFF 7DFF FFFF 1F80 0000 to 7E00 0000 to 1FFF FFFF 7FFF FFFF 7­20 Registers FADR·Failing Address Register Table 7­14 FADR Register Bit Definitions NOTE: The FADR register does not capture the entire LSB address. It drops ad­ dress bits D<34:32>. Address Access BB + 2100 RO The FADR register contains the failing 32­bit LSB address any time the 64­bit ECC logic detects an ECC error during memory reads. This register is locked upon either a correctable or uncorrectable ECC error. Name Bit(s) Type Function FADR <31:0> RO Failing Address. Contains the LSB address driven on D<31:0> during a command/address cycle. The failing address bits are saved when the memory in­ terface controller detects either a correctable or uncorrectable ECC error within the 64­bit ECC logic during LSB memory read transactions. If this field is already locked with the failing address of a correctable ECC error when an uncorrectable ECC error occurs, it is updated with the failing address of the uncorrectable error. Registers 7­21 MERA·Memory Error Register A Table 7­15 MERA Register Bit Definitions Address Access BB + 2140 R/W The MERA register provides additional error information about node­specific error conditions that are captured in the MIC­A. This register includes two bits that, when set, indicate the occur­ rence of an error on the MIC­B. Name Bit(s) Type Function RSVD <31:12> R0 Reserved. Read as zero. 7­22 Registers Table 7­15 MERA Register Bit Definitions (Continued) Name Bit(s) Type Function UCERB UCERA BNKER FSTR CERB <11> <10> <9> <8:6> <5> W1C, 0 W1C, 0 W1C, 0 RO, 0 W1C, 0 Uncontrollable Error on MIC­B. Set when MIC­ B detects an uncorrectable 64­bit ECC error. The high state of this bit locks bits <8:6> of this register and the contents of the FADR register. It also blocks UCERA (MERA<10>) from being set. If MIC­A and MIC­B were to detect simultaneous 64­ bit ECC errors, then either bits <11> and <10>, or bits <5> and <4> would be set at the same time. The failing string and the address in the FADR reg­ ister would pertain to failures detected in both MIC­ A and MIC­B. If either MIC­A or MIC­B detects an error, then the setting of the appropriate bit and the blocking of the other bit in the combination allows isolation of independent failures on MIC­A or MIC­ B to the failing string and LSB address. Uncorrectable Error on MIC­A. Set when MIC­ A detects an uncorrectable 64­bit ECC error. The high state of this bit locks bits <8:6> of this register and the contents of the FADR register. It also blocks UCERB (MERA<11>) from being set. See de­ scription of UCERB above. Bank Conflict Error. When set, indicates that an LSB request was made to a currently active memory bank. When this bit is set, LSB ERR is asserted. Failing String. Indicates which of the eight strings were being accessed during an LSB memory read when an uncorrectable or correctable ECC er­ ror was detected by memory's 64­bit ECC logic. This field, along with the two syndrome registers, iso­ lates single­bit errors to a failing DRAM component. FSTR is locked when a correctable or uncorrectable error bit is set in either MIC­A or MIC­B. If this field is already locked with the failing address of a correctable ECC error when an uncorrectable ECC error occurs, it is updated with the failing address of the uncorrectable error. Correctable ECC Error on MIC­B. Set when a correctable ECC error is detected on MIC­B. The high state of this bit locks bits <8:6> of this register and the contents of the FADR register. It also blocks CERA MERA<4>) from being set. See de­ scription of UCERB (MERA<11>) above. Registers 7­23 Table 7­15 MERA Register Bit Definitions (Continued) Name Bit(s) Type Function CERA APER MULE UCER CER <4> <3> <2> <1> <0> W1C, 0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 Correctable ECC Error on MIC­A. Set when a correctable ECC error is detected on MIC­A. The high state of this bit locks bits <8:6> of this register, the contents of the FADR register and the contents of the MSYNDA register. It also blocks CERB (MERA<5>) from being set. See description of UCERB (MERA<11>) above. Address Parity Error. Set when a row or column address parity error is detected. If APER is set, UCERA (MERA<1>) is also set. Multiple Errors. Set when a second correctable or uncorrectable error is detected after either UCER (MERA<1>) or CER (MERA<0>) has been set. This bit sets only if an error is detected on a subsequent read transaction. It does not set if multiple errors are detected within the same transaction. Uncorrectable Read Error. Set when an uncorrectable read data error is detected within memory's 64­bit ECC logic protecting D<63:0>. Mem­ ory supplies the data with uncorrectable errors forced on LSB check bits ECC<13:0>. When this bit sets, the Memory Error Syndrome Register A is locked with the failing syndrome. Correctable Read Error. Set when a correctable read data error is detected within memory's 64­bit ECC logic protecting D<63:0>. Memory corrects the data in error and supplies good data to LSB. When this bit sets, the Memory Error Syndrome Register A is locked with the failing syndrome. 7­24 Registers MSYNDA·Memory Error Syndrome Register A Table 7­16 MSYNDA Register Bit Definitions Address Access BB + 2180 RO The MSYNDA register is used to determine which bit is in error when a correctable ECC error is detected by the module during an LSB memory read transaction. This register contains the syn­ drome bits generated by memory's 64­bit ECC logic protecting D<63:0>. The error syndrome is decoded by software to the bit in error so that it can be logged accordingly. This register is locked when either a correctable read error bit (CER) or an uncorrectable read error bit (UCER) is set in the MERA register. MSYNDA is unlocked when the error bit or bits are cleared in the MERA regis­ ter. If this register is already locked with the failing syndrome of a correctable ECC error when an uncorrectable ECC error occurs, it is updated with the uncorrectable error syndrome. Name Bit(s) Type Function RSVD SYNDA <31:8> <7:0> R0 RO, 0 Reserved. Read as zero. Syndrome A. Contains the error syndrome protect­ ing D<63:0>. Registers 7­25 MDRA·Memory Diagnostic Register A Table 7­17 MDRA Register Bit Definitions Address Access BB + 21C0 R/W The MDRA register is used by diagnostics to help isolate failures and to force specific error conditions within the module and the MIC­A chip. When MDRA is written, MDRB<7:0> are written con­ currently. This feature allows syncronization of diagnostic opera­ tions between MIC­A and MIC­B. Bits<7:0> of MDRA and MDRB registers have one­to­one matching functions. NOTE: This register is reserved for Digital use. Name Bit(s) Type Function DRFSH <31> R/W, 0 Disable Refresh. If set, "on­board" refresh of the module is disabled and diagnostic burst refresh (see BRFSH, MDRA<30>) is enabled. When this bit is set concurrently with BRFSH, a burst refresh cycle is executed. 7­26 Registers Table 7­17 MDRA Register Bit Definitions (Continued) Name Bit(s) Type Function BRFSH RFR DCRD RSVD FCPE FRPE IGSB MODE <30> <29:28> <27> <26:10> <9> <8> <7> <6> WO, 0 R/W, 0 R/W, 0 R0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 Burst Refresh. When BRFSH is set, and DRFSH (MDRA<31>) is also set, a single row address within the accessed DRAMs is refreshed as per CAS before RAS refresh operation. When this bit is set concur­ rently with DRFSH, a burst refresh cycle is executed. Refresh Rate. Determines the refresh rate of the module. Disable CRD Assertion. If set, LSB_CRD does not assert when memory detects a read CRD error in the 64­bit ECC logic. Reserved. Read as zero. Force Column Parity Error. If set, incorrect col­ umn address parity is written into the addressed lo­ cation in memory. Force Row Parity Error. If set, incorrect row ad­ dress parity is written into the addressed location in memory. Ignore Single­Bit Self­Test Failures. If set, self­ test logic does not report errors in the MSTR0/ MSTR1 registers when a single bit is detected to be in error for each octaword read. Only errors of two or more bits are reported. Self­Test Mode. If set, self­test executes a defined "ones/zeros" data pattern when running under diag­ nostic control. Two passes are executed. In the first pass, all data bits in an odd hexword address are written with ones, while those in an even hexword are written with zeros. In the second pass, hexword addresses are written with inverse data patterns. MDRA<29:28> Refresh Rate 00 01 10 11 1 x default 2 x default 4 x default Reserved Registers 7­27 Table 7­17 MDRA Register Bit Definitions (Continued) Name Bit(s) Type Function STPM EXST BPAS DWDC DRDC FCBS <5> <4> <3> <2> <1> <0> R/W, 0 R/W, 1 R/W, 0 R/W, 0 R/W, 0 R/W, 0 Self­Test Pause Mode. If set, self­test completes one of its three passes. To execute the next pass, EXST (MDRA<4>) must be set. This feature is neces­ sary for memory manufacturing tests. STPM must be set at the start of each pass. Otherwise, self­test begins at pass 1. Execute Self­Test. If EXST is set, memory self­test is invoked. The self­test logic examines this bit to de­ termine if self­test should be executed. This bit is set upon system power­up or LSB reset. It is cleared when self­test completes execution. It is also cleared in diagnostic mode when STPM is set for each pass that the self­test state machine completes. Bypass. If set, both the read data path and write data path ECC logic is bypassed to aid in memory manufacturing tests. LSB ECC<7:0> is directly mapped to the eight ECC check bits protecting D<63:0> in the MIC­A. Disable Write Data Correction. If set, ECC cor­ rection of LSB memory write data is disabled. Uncor­ rected data is written to memory with a no error ECC check bit code. The setting of this bit affects the correction of D<63:0>. Thirty­two bit ECC er­ rors, if present, are logged. Disable Read Data Correction. If set, ECC correc­ tion of memory read data is disabled. The setting of this bit affects the correction of D<63:0>. Force Check Bit Substitution. If set, the con­ tents of the MCBSB register is gated into the 64­bit write ECC logic in place of the DRAM check bits. The setting of this bit affects D<63:0>. 7­28 Registers MCBSA·Memory Check Bit Substitute Register A Table 7­18 MCBSA Register Bit Definitions Address Access BB + 2200 R/W The MCBSA register is used to check the 64­bit ECC logic on the memory module during memory read transactions. This register is first loaded by diagnostics with substitute bits for DRAM check bits. The contents of the MCBSA register is then written to a se­ lected memory location. When the write transaction is complete, each of the four octawords contains the substituted check bits and data issued on the bus. The location in memory written with sub­ stitute check bits will contain an UNDEFINED ECC code. Soft­ ware executing such tests must ensure that memory is initialized to good ECC by reexecuting self­test or by other means. Name Bit(s) Type Function RSVD SCB_A <31:8> <7:0> R0 R/W, 0 Reserved. Read as zero. Substituted Check Bits A. SCB_A is used in place of the DRAM check bits protecting D<63:0> when DRDC (MDRA <1>) is set. Registers 7­29 MERB·Memory Error Register B Address Access BB + 4140 R/W The MERB register provides additional error information about node­specific error conditions that are captured in the MIC­B chip. 7­30 Registers Table 7­19 MERB Register Bit Definitions Name Bit(s) Type Function RSVD APER MULE UCER CER <31:4> <3> <2> <1> <0> R0 W1C, 0 W1C, 0 W1C, 0 W1C, 0 Reserved. Read as zero. Address Parity Error. Set when a row or column address parity error is detected. If APER is set, UCER (MERB<1>) is also set. Multiple Errors. Set when a second correctable or uncorrectable error is detected after either UCER (MERB<1>) or CER (MERB<0>) has been set. This bit sets only if an error is detected on a subsequent read transaction. It does not set if multiple errors are detected within the same transaction. Uncorrectable Read Error. Set when an uncorrectable read data error is detected within memory's 64­bit ECC logic protecting D<127:64>. Memory supplies the data with uncorrectable errors forced on LSB check bits ECC<27:14>. When this bit sets, the Memory Error Syndrome Register A is locked with the failing syndrome. Correctable Read Error. Set when a correctable read data error is detected within memory's 64­bit ECC logic protecting D<127:64>. Memory corrects the data in error and supplies good data to the LSB. When this bit sets, the Memory Error Syndrome Register B is locked with the failing syndrome. Registers 7­31 MSYNDB·Memory Error Syndrome Register B Table 7­20 MSYNDB Register Bit Definitions Address Access BB + 4180 RO The MSYNDB register is used to determine which bit is in error when a correctable ECC error is detected by the module during an LSB memory read transaction. This register contains the syn­ drome bits generated by memory's 64­bit ECC logic protecting D<63:0>. The error syndrome is decoded by software to the bit in error so that it can be logged accordingly. This register is locked when either a correctable read error bit (CER) or an uncorrectable read error bit (UCER) is set in the MERB register. MSYNDB is un­ locked when the error bit or bits are cleared in the MERB register. If this register is already locked with the failing syndrome of a correctable ECC error when an uncorrectable ECC error occurs, it is updated with the uncorrectable error syndrome. Name Bit(s) Type Function RSVD SYNDB <31:8> <7:0> R0 RO, 0 Reserved. Read as zero. Syndrome B. Contains the error syndrome protect­ ing D<127:64>. 7­32 Registers MDRB·Memory Diagnostic Register B Table 7­21 MDRB Register Bit Definitions Address Access BB + 41C0 R/W The MDRB register is used by diagnostics to help isolate failures and to force specific error conditions within the module and the MIC­B chip. When the MDRA register is written, MDRB<7:0> are written concurrently. This feature allows syncronization of diag­ nostic operations between MIC­A and MIC­B. Bits<7:0> of MDRA and MDRB registers have one to one matching functions. NOTE: This register is reserved for Digital use. Name Bit(s) Type Function RSVD IGSB <31:8> <7> R0 R/W, 0 Reserved. Read as zero. Ignore Single­Bit Self­Test Failures. If set, self­ test logic does not report errors in the MSTR0/ MSTR1 registers when a single bit is detected to be in error for each octaword read. Only errors of two or more bits are reported. Registers 7­33 Table 7­21 MDRB Register Bit Definitions (Continued) Name Bit(s) Type Function MODE STPM EXST BPAS DWDC DRDC FCBS <6> <5> <4> <3> <2> <1> <0> R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0 Self­Test Mode. If set, self­test executes a defined "ones/zeros" data pattern when running under diag­ nostic control. Two passes are executed. In the first pass, all data bits in an odd hexword address are written with ones, while those in an even hexword are written with zeros. In the second pass, hexword addresses are written with inverse data patterns. Self­Test Pause Mode. If set, self­test completes one of its three passes. To execute the next pass, EXST (MDRB<4>) must be set. This feature is nec­ essary for memory manufacturing tests. STPM must be set at the start of each pass. Otherwise, self­test begins at pass 1. Execute Self­Test. If EXST is set, memory self­ test is invoked. The self­test logic examines this bit to determine if self­test should be executed. This bit is set upon system power­up or LSB reset. It is cleared when self­test completes execution. It is also cleared in diagnostic mode when STPM is set for each pass that self­test completes. Bypass. If set, both the read data path and write data path ECC logic is bypassed to aid in memory manufacturing tests. LSB ECC<15:8> is directly mapped to the eight ECC check bits protecting D<127:64> in the MIC­B chip. Disable Write Data Correction. If set, ECC cor­ rection of LSB memory write data is disabled. Un­ corrected data is written to memory with a no error ECC check bit code. The setting of this bit affects the correction of D<127:64>. Thirty­two bit ECC er­ rors, if present, are logged. Disable Read Data Correction. If set, ECC cor­ rection of memory read data is disabled. The setting of this bit affects the correction of D<127:64>. Force Check Bit Substitution. If set, the con­ tents of the MCBSB register is gated into the 64­bit write ECC logic in place of the DRAM check bits. The setting of this bit affects D<127:64>. 7­34 Registers MCBSB·Memory Check Bit Substitute Register B Table 7­22 MCBSB Register Bit Definitions Address Access BB + 2200 R/W The MCBSB register is used to check the 64­bit ECC logic on the memory module during memory read transactions. This register is first loaded by diagnostics with substitute bits for DRAM check bits. The contents of the MCBSB register is then written to a se­ lected memory location. When the write transaction is complete, each of the four octawords contains the substituted check bits and data issued on the bus. The location in memory written with sub­ stitute check bits will contain an UNDEFINED ECC code. Soft­ ware executing such tests must ensure that memory is initialized to good ECC by reexecuting self­test or by other means. Name Bit(s) Type Function RSVD SCB_B <31:8> <7:0> R/W, 0 R/W, 0 Reserved. Read as zero. Substituted Check Bits B. SCB_B is used in place of the DRAM check bits protecting D<127:64> when DRDC (MDRB <1>) is set. Error Conditions 8­1 Chapter 8 Error Conditions The memory module detects two categories of ECC errors: · Memory­related LSB errors · Memory­specific errors This chapter describes the two types of errors and explains how they are reported in error syndrome registers. 8.1 Memory­Related LSB Errors In general, memory responds as follows to LSB errors it detects during memory read or write transactions: · Command/Address Cycles Memory reports parity errors that it detects during command/address cycles and captures the contents of D<38:0> in the LBECR0 and LBECR1 registers. It does not act on the command or the address. · CSR Write Data Cycles Memory does not write CSR data to the specified memory CSR when a parity error is detected. Memory asserts LSB ERR. · Memory Write Data Cycles If a single­bit ECC error is detected on memory write data, the bit in error is corrected before data is written to memory. If an uncorrectable ECC error is detected on memory write data, no correction is made to the data. The bad data is written to memory along with an uncorrectable ECC code forced on the 64­bit ECC check bits. · Memory Read Data Cycles See memory­specific ECC errors in the MERA and MERB registers. 8.2 Memory­Specific Errors Memory­specific errors relate to the 64­bit ECC logic that protects the DRAM array. These errors are reported in Memory Error Register A (MERA) and Memory Error Register B (MERB). Memory­specific errors are detected only during LSB memory reads. 8.3 Error Syndrome Decoding On the LSB bus, data is protected by 32­bit ECC error logic. However, on the memory module, error logic implements a 64­bit ECC. Therefore, con­ version of quadword (64­bit) ECC to longword (32­bit) ECC must be per­ 8­2 Error Conditions formed on memory read data. Conversely, longword to quadword ECC is performed on memory write data. The conversion logic is implemented on the MIC. 8.3.1 Quadword Memory Error Syndrome Decoding When an ECC error is detected by the 64­bit memory ECC logic, the error syndrome registers MSYNDA/MSYNDB are locked. Each of these regis­ ters contains the error syndrome associated with a failure in either the MERA register or the MERB register. If a correctable or uncorrectable error bit is set, the error syndrome regis­ ter will contain the failing syndrome. If the error is correctable, logging software can use this information to determine the bit in error and log it appropriately. This information is of little use, however, if the error is uncorrectable. Table 8­1 shows the 64­bit ECC codes used, with associated check bits for each of the 64 data bits. Error logging software can use this table to deter­ mine the bit in error whenever single­bit errors are detected. Table 8­1 Quadword Error Syndrome Table MIC­A Bit in Error MIC­B Bit in Error Syndrome Value (Hex) No Error 0 1 2 3 4 5 6 7 8 9 10 No Error 64 65 66 67 68 69 70 71 72 73 74 00 13 23 43 83 2F F1 0D 07 D0 70 4F Error Conditions 8­3 Table 8­1 Quadword Error Syndrome Table (Continued) MIC­A Bit in Error MIC­B Bit in Error Syndrome Value (Hex) 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 F8 61 62 64 68 1C 2C 4C 8C 15 25 45 85 19 29 49 89 1A 2A 4A 8A 51 52 54 58 91 92 94 98 A1 A2 A4 A8 31 32 34 38 16 26 46 89 1F F2 0B 0E 8­4 Error Conditions Table 8­1 Quadword Error Syndrome Table (Continued) 8.3.2 Longword Memory Error Syndrome Decoding When an ECC error is detected by the LSB ECC logic, the error syndrome registers LBESR03 are locked. Each of these registers contains the error syndrome associated with a failure as seen on the LSB bus. If a correctable or uncorrectable error bit is set, the error syndrome regis­ ter will contain the failing syndrome. If the error is correctable, logging software can use this information to determine the bit in error and log it appropriately. This information is of little use, however, if the error is uncorrectable. Table 8­2 shows the 32­bit ECC codes used, with associated check bits for each of the 32 data bits. Error logging software can use this table to deter­ mine the bit in error whenever single­bit errors are detected. MIC­A Bit in Error MIC­B Bit in Error Syndrome Value (Hex) 56 57 58 59 60 61 62 63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Row Parity Column Parity 120 121 122 123 124 125 126 127 CB8 CB9 CB10 CB11 CB12 CB13 CB14 CB15 FD FE B0 E0 8F F4 C1 C2 C4 C8 01 02 04 08 10 20 40 80 Error Conditions 8­5 Table 8­2 Longword LSB Error Syndrome Table MIC­A Bit in Error MIC­B Bit in Error Syndrome Value (Hex) No Error 0,32 1,33 2,34 3,35 4,36 5,37 6,38 7,39 8,40 9,41 10,42 11,43 12,44 13,45 14,46 15,47 16,48 17,49 18,50 19,51 20,52 21,53 22,54 23,55 24,56 25,57 26,58 27,59 28,60 29,61 30,62 31,63 CB0,CB7 CB1,CB8 CB2,CB9 CB3,CB10 CB4,CB11 CB5,CB12 CB6,CB13 Cycle­0 Cycle­1 No Error 64,96 65,97 66,98 67,99 68,100 69,101 70,102 71,103 72,104 73,105 74,106 75,107 76,108 77,109 78,110 79,111 80,112 81,113 82,114 83,115 84,116 85,117 86,118 87,119 88,120 89,121 90,122 91,123 92,124 93,125 94,126 95,127 CB14,CB21 CB15,CB22 CB16,CB23 CB17,CB24 CB18,CB25 CB19,CB26 CB20,CB27 7A 79 00 4F 4A 52 54 57 58 5B 5D 23 25 26 29 2A 2C 31 34 0E 0B 13 15 16 19 1A 1C 62 64 67 68 6B 6D 70 75 01 02 04 08 10 20 40 Self­Test 9­1 Chapter 9 Self­Test The memory self­test performs a quick testing of the DRAM array and re­ cords sections of the array that contain defective locations. This occurs automatically at system power­up upon assertion of LSB RESET. Self­ test may be invoked by setting EXST (MDRA/MDRB<4>) through a con­ sole deposit command. 9.1 Self­Test Report When the memory module starts self­test, it sets STF (LCNR<31>). The memory self­test does not provide a pass/fail status. It flags the defective segments in memory by setting associated bits in the MSTR0 and MSTR1 registers (see Table 7­13) and clears EXST and STF when it is done. Clearing of STF lights the module LED, indicating the completion of the test procedures. Address segments are mapped according to the module's total possible ca­ pacity (maximum of 8 strings), not to the actual memory capacity imple­ mented on the module. For example, the maximum possible capacity of a memory module using 4­Mbit DRAMs is 512 Mbytes (2 Gbytes for 16­ Mbit DRAMs). In this configuration, each bit in the MSTR0 and MSTR1 registers is associated with an 8­Mbyte segment of memory (32 Mbytes for 16­Mbit DRAMs). Bit zero of MSTR0 describes an address segment from 0 to 8 Mbytes (0 to 32 Mbytes for 16­Mbit DRAMs); bit one describes an address segment from 8 to 16 Mbytes (32 to 64 Mbytes for 16­bit DRAMs), and so on. 9.2 Self­Test Modes Self­test can be conducted in several different operating modes selected by configuring the MDRA and MDRB registers. One mode of operation causes the self­test logic to ignore all single­bit errors. When this mode is selected, single­bit failures do not set any of the 64 address segment bits in MSTR0 or MSTR1. However, if a multiple­bit error is detected in a memory segment, the associated address segment is set. By default, single­bit errors are recorded in MSTR0 and MSTR1. 9­2 Self­Test 9.3 Self­Test Performance The duration of the memory self­test is affected by the following parame­ ters: · Memory array capacity · Memory array architecture · DRAM size · DRAM speed The capacity of the memory module is the main factor that determines the length of self­test. Table 9­1 shows self­test times for memory modules of different capacities. Table 9­1 Memory Self­Test Times Module Capacity (Mbytes) Self­Test Duration (Seconds) 4­Mbit DRAM 16­Mbit DRAM 64 128 256 512 1024 2028 1.3 N/A1 1.3 N/A 2.7 5.4 5.4 5.4 N/A 10.7 N/A 21.4 1 Not applicable. Index­1 Index A Acronyms, bit access type, 7­2 Addresses, node space base, 7­1 Address decode logic, 2­2 Address Mapping Register, 7­14 Address Parity Error, 7­23, 7­30 Address Width, 7­15 AMR, 7­14 APER, 7­23, 7­30 Arbitration request, 5­2 Array capacity, 4­1 AW, 7­15 B Banking, memory, 4­1 Bank Conflict Error, 7­22 Base addresses, 7­1 Bit designations, viii Block diagram, 1­2 BNKER, 7­22 BPAS, 7­27, 7­33 BRFSH, 7­26 Burst Refresh, 7­26 Bus Error Register, 7­5 Bypass, 7­27, 7­33 C CA, 5­2, 7­10, 7­11 CAE, 7­6 Capacity, memory, 4­1 CDPE, 7­6 CDPE2, 7­6 CE, 7­6 CEEN, 7­7 CER, 7­23, 7­30 CERA, 7­23 CERB, 7­22 CE2, 7­6 CID, 7­11 CMD, 7­11 CNF, 5­2, 7­11 CNFE, 7­6 CNF Error, 7­6 Command, 7­11 Commander ID, 7­11 Commands, 2­2 Command decode logic, 2­2 Command Parity Error, 7­6 Command/Address, 5­2, 7­10, 7­11 Command/Address Error, 7­6 Configuration Register, 7­7 Confirmation, 5­2, 7­11 Control Transmit Check Error, 7­6 Conventions, viii Conversion, ECC, 6­2 Correctable Data Error, 7­6 Correctable ECC Error on MIC­A, 7­23 Correctable ECC Error on MIC­B, 7­22 Correctable Error Detection Enable, 7­7 Correctable Read Error, 7­23, 7­30 CPE, 7­6 CPE2, 7­6 CSR Data Parity Error, 7­6 CTCE, 7­6 Cycle times, 2­4 D Data, 5­2 Data cycle, 7­10 Data path, MDC, 3­1 Data Transmit Check Error, 7­6 Data wrapping, 2­4 DCRD, 7­26 DCYCLE, 7­10 Default Interleave, 4­3 Device Register, 7­4 Device revision, 7­4 Device Type, 7­13 DIE, 7­6 DIRTY, 5­2, 7­11 Disable CRD Assertion, 7­26 Disable Read Data Correction, 7­27, 7­33 Disable Refresh, 7­25 Disable Write Data Correction, 7­27, 7­33 DRAM address logic, 2­3 DRAM arrays, 1­3 DRAM control logic, 2­3 Index­2 DRDC, 7­27, 7­33 DREV, 7­4 DRFSH, 7­25 DTCE, 7­6 DTYP, 7­13 DTYPE, 7­4 DWDC, 7­27, 7­33 E E, 7­6, 7­16 ECC, 5­2 ECC conversion, 6­2 Enable, 7­16 ERR, 5­2 Error, 5­2 Errors, memory­related, 8­1 Errors, memory­specific, 8­1 Error address segments, 7­18, 7­19 Error bit, 7­6 Error checking and correction, 5­2 Error Command Register, 7­10 Error conditions, 8­1 Error Register, Bus, 7­5 Error syndrome decoding, 8­1 Error syndrome decoding, longword, 8­4 Error syndrome decoding, quadword, 8­2 Error Syndrome Register, 7­9 Execute self­test, 7­27 Execute Self_Test, 7­33 EXST, 7­27, 7­33 F FADR, 7­20 Failing Address, 7­20 Failing Address Register, 7­20 FCBS, 7­27, 7­33 FCPE, 7­26 Force Check Bit Substitution, 7­27, 7­33 Force Column Parity Error, 7­26 Force Row Parity Error, 7­26 FRPE, 7­26 FSTR, 7­22 I IA, 7­16 IBR, 7­8 Ignore Single­Bit Self­Test Failures, 7­32 IGSB, 7­26, 7­32 Information Base Register, 7­8 Interleave, 4­3, 7­16 Interleave Address, 7­16 Interleaving, 4­2 Internal buses, 1­3 INTL, 7­16 L LBECR, 7­10 LBER, 7­5 LBESR, 7­9 LCNR, 7­7 LDEV, 7­4 Logic address decode, 2­2 command decode, 2­2 DRAM address, 2­3 DRAM control, 2­3 LSB state machine, 2­5 MIC data path, 2­3 refresh, 2­4 self­test, 2­5 Longword error syndrome decoding, 8­4 LSB CA, 5­3 LSB CNF, 5­3 LSB commands, 2­2 LSB cycle times, 2­4 LSB DIRTY, 5­3 LSB ERR, 5­3 LSB errors, memory­related, 8­1 LSB memory signals, 5­1 LSB NID, 5­3 LSB PH0, 5­3 LSB REQ, 5­4 LSB RESET, 5­4 LSB STALL, 5­4 LSB state machine control logic, 2­5 M MADR, 7­14 MCBSA, 7­28 MCBSB, 7­34 MCR, 7­12 MDC, 3­1 MDC data path, 3­1 MDC transactions, 3­1 MDC wrap ordering, 3­2 MDRA, 7­25 MDRB, 7­32 Memory banking, 4­1 Memory block diagram, 1­2 Memory capacity, 4­1 Memory Check Bit Substitution A, 7­28 Memory Check Bit Substitution B, 7­34 Memory Configuration Register, 7­12 Memory data controller, 1­3, 3­1 Memory Diagnostic Register A, 7­25 Memory Diagnostic Register B, 7­32 Memory Error Register A, 7­21 Memory Error Register B, 7­29 Memory Error Syndrome Register A, 7­24 Memory Error Syndrome Register B, 7­31 Index­3 Memory interface controller, 1­2, 2­1 Memory interleaving, 4­2 Memory module overview, 1­1 Memory organization, 4­1 Memory refresh, 1­3 Memory Self­Test Register, 7­17 Memory signals, 5­1 Memory space transactions, 2­3 Memory transactions, 6­1 ordering, 6­2 read, 6­1 write, 6­1 Memory­related LSB errors, 8­1 Memory­specific errors, 8­1 MERA, 7­21 MERB, 7­29 MIC, 2­1 MIC data path logic, 2­3 MODE, 7­26, 7­33 Module Address, 7­14 Module block diagram, 1­2 MSTR, 7­17 MSYNDA, 7­24 MSYNDB, 7­31 MULE, 7­23, 7­30 Multiple Errors, 7­23, 7­30 N NBANKS, 7­15 NHALT, 7­7 NID, 5­2 Node Halt, 7­7 Node ID, 5­2 Node Reset, 7­7 Node space base addresses, 7­1 Node space CSR transactions, 2­2 Node­Specific Error Summary, 7­6 Nonexistent address error, 7­6 NRST, 7­7 NSES, 7­6 Number of Banks, 7­15 NXAE, 7­6 O Ordering, MDC wrap, 3­2 Ordering, memory transactions, 6­2 Overview, 1­1 P Parity, 7­11 PH0 (SINE), 5­2 Q Quadword error syndrome decoding, 8­2 R RCV_SDAT, 7­8 Read transactions, 3­1, 6­1 Receive Serial Data, 7­8 Refresh logic, 2­4 Refresh RAM, 1­3 Refresh Rate, 7­26 Refresh rates, 2­4 Register Address Mapping, 7­14 Bus Error, 7­5 Configuration, 7­7 descriptions, 7­3 Device, 7­4 Error Command, 7­10 Error Syndrome, 7­9 Failing Address, 7­20 Information Base Repair, 7­8 Memory Check Bit Substitution A, 7­28 Memory Check Bit Substitution B, 7­34 Memory Configuration, 7­12 Memory Diagnostic A, 7­25 Memory Diagnostic B, 7­32 Memory Error A, 7­21 Memory Error B, 7­29 Memory Error Syndrome A, 7­24 Memory Error Syndrome B, 7­31 Memory Self­Test, 7­17 table, 7­3 Registers, 7­1 Register bit designations, viii REQ, 5­2 RESET, 5­2 Reset Status, 7­7 RFR, 7­26 RSTSTAT, 7­7 S SCB_A, 7­28 SCB_B, 7­34 SCLK, 7­8 Second Command Parity Error, 7­6 Second Correctable Data Error, 7­6 Second CSR Parity Error, 7­6 Second Uncorrectable Data Error, 7­6 Segments, memory error address, 7­18, 7­19 Self­Test, 9­1 Self­Test Fail, 7­7 Self­Test Failing Address Segment, 7­17 Self­Test logic, 2­5 Self­Test Mode, 7­26, 7­33 Self­test modes, 9­1 Self­Test Pause Mode, 7­27, 7­33 Self­test performance, 9­2 Self­test report, 9­1 Index­4 Self­test times, 9­2 Serial Clock, 7­8 SHARED, 7­11 SHARED Error, 7­6 SHE, 7­6 Signal descriptions LASB RESET, 5­4 LSB CA, 5­3 LSB CNF, 5­3 LSB Data D<127:0>, 5­1 LSB DIRTY, 5­3 LSB ERR, 5­3 LSB NID, 5­3 LSB PH0, 5­3 LSB REQ, 5­4 LSB STALL, 5­4 Sine, 5­2 STALL, 5­2 Stalled read transactions, 6­1 Stalled write transactions, 6­2 STALL Error, 7­6 STE, 7­6 STF, 7­7 STFAS, 7­17 STPM, 7­27, 7­33 STRG, 7­13 String, 7­13 Substituted Check Bits A, 7­28 Substituted Check Bits B, 7­34 SYDROME_0, 7­9 SYDROME_1, 7­9 SYDROME_2, 7­9 SYDROME_3, 7­9 SYNDA, 7­24 SYNDB, 7­31 Syndrome A, 7­24 Syndrome B, 7­31 System interleave, 4­3 T TDE, 7­6 Terminology, ix Transactions memory, 6­1 memory read, 6­1 memory space, 2­3 node space CSR, 2­2 read, 6­1 wrapped read, 3­1 wrapped write, 3­2 write, 6­1 Transaction ordering, 6­2 Transmitter During Error, 7­6 Transmit Serial Data, 7­8 U UCE, 7­6 UCER, 7­23, 7­30 UCERA, 7­22 UCERB, 7­22 UCE2, 7­6 Uncorrectable Data Error, 7­6 Uncorrectable Error on MIC­A, 7­22 Uncorrectable Error on MIC­B, 7­22 Uncorrectable Read Error, 7­23, 7­30 W Wrapped read transactions, 3­1 Wrapped write transactions, 3­2 Wrapping, data, 2­4 Write transactions, 6­1 X XMT_SDAT, 7­8