VSXXX-DA Dial Array Technical Manual Order Number: EK-VSXDA-TM-001 February 1988 digital equipment corporation maynard, massachusetts ___________________________________________________ February 1988 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. The software described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license. Digital Equipment Corporation assumes no responsi- bility for the use or reliability of its software on equipment that is not supplied by Digital or its affiliated companies. Copyright (c)1988 by Digital Equipment Corporation All Rights Reserved ___________________________________________________ Printed in U.S.A. USA This equipment generates, uses, and may emit radio frequency energy. The equipment has been type tested and found to comply with the limits for a Class A computing device pursuant to Subpart J of Part 15 of FCC Rules, which are designed to provide reasonable protection against such radio frequency interference. Operation of this equipment in a residential area may cause interference in which case the user at his own expense will be required to take whatever measures may be required to correct the interference. ___________________________________________________ The following are trademarks of Digital Equipment Corporation: DEC ULTRIX VAXstation DECnet ULTRIX-32 VMS DECUS UNIBUS VT MicroVAX VAX MicroVMS VAXBI DIGITAL PDP VAXcluster Chapter 1 Physical Characteristics _______________________________________________________ The VSXXX-DA dial array (Figure 1-1) is a microprocessor- controlled interactive peripheral device for graph- ics workstations such as the VAXstation 8000 work- station. It provides eight optical shaft encoders that change various parameters of the graphics object on the display. Each shaft encoder has an associated segmented-LED display (this combination is also called an encoder/LED set). The dial array interface to the workstation is through a concentrator such as the VSXXX-CA/CB Peripheral Repeater. The dial array is also called the dial box or knobs box. Tables 1-1, 1-2, and 1-3 list the physical, electrical, and environmental specifications of the dial array. Physical Characteristics 1-1 Figure 1-1: Dial Array Pictorial of the dial array ____________________________________________________ Table 1-1: Physical Specifications ____________________________________________________ Parameter Specification Height 8.00 cm (3.15 in) Width 29.20 cm (11.50 in) Depth 17.20 cm (6.80 in) Weight 1.13 kg (2.50 lb) ____________________________________________________ 1-2 Physical Characteristics ____________________________________________________ Table 1-2: Electrical Specifications ____________________________________________________ Parameter Specification Power 10.00 W (typical) 15.00 W (maximum) Current 2.00 A (typical) 3.00 A (maximum) Voltage +5.00 +0.25 Vdc ____________________________________________________ ____________________________________________________ Table 1-3: Environmental Specifications ____________________________________________________ Parameter Specification Operating Temperature 10o to 40o C (50o Altitude to 104o F)[1] Relative humidity 2.4 km (8000 ft) Maximum wet-bulb tempera- maximum ture 10% to 90% (noncondensing) 28o C (82.4o F) Nonoperating Temperature -40o to 66o C (- Altitude 40o to 151o F) Relative humidity 4.9 km (16000 ft) Minimum dew-point tempera- typical ture 10% to 95% (noncondensing) 2o C (36o F) ____________________________________________________ [1]De-rate maximum operating temperature 1.82o C/km (1.0o F/1000 ft) above sea level. Physical Characteristics 1-3 ____________________________________________________ Table 1-3 (Continued): Environmental Specifications ____________________________________________________ Parameter Specification Storage Temperature 5o to 50o C (41o Relative humidity to 122o F) Maximum wet-bulb tempera- 10% to 95% ture (noncondensing) 32o C (90o F) Heat dissipation Typical: 10 W, 34.1 Btu/h Maximum: 15 W, 51.2 Btu/h ____________________________________________________ 1-4 Physical Characteristics Chapter 2 Functional Description _______________________________________________________ This chapter gives a functional description of the dial array hardware and firmware. 2.1 Hardware Figure 2-1 is a block diagram of the dial array. All electronics are contained on three modules: a logic board and identical upper and lower display boards. The logic board is the dial array controller; it provides the interface to the VSXXX-CA/CB Peripheral Repeater. All dial array functions, except alphanumeric display, are performed by the logic board. As Figure 2-1 shows, the major functional components of the dial array include: _ CPU _ The central processing unit is a 68000 micropro- cessor. It controls most of the other dial array functions. _ ADDRESS LINES _ Functional Description 2-1 The address lines consist of the lowest 15 bits of the CPU's 23 address bits and address and enable various functions. _ DATA LINES _ The data lines consist of 16 bidirectional lines. With the exception of the CPU, most devices usually read and/or write either the upper or the lower byte. 2-2 Functional Description Figure 2-1: Dial Array Block Diagram ASD-1189 Functional Description 2-3 _ ROM _ Read-only memory consists of two 8-kbyte (8k x 8) ROMs. These ROMs contain all the dial array operational firmware and self-test diagnostics. _ RAM _ Random-access memory consists of two 2-kbyte (2k x 8) static RAMs (SRAMs). These RAMs are used as a scratch pad and for stack operations. _ DUART _ This dual universal asynchronous receiver/transmitter performs serial-to-parallel and parallel-to- serial data conversion for external serial communications. _ OPTICAL SHAFT ENCODERS _ Eight optical shaft encoders provide the input part of the dial array's human interface. _ QUADRATURE DECODERS _ Eight quadrature decoders convert shaft encoder input from pulse-train to parallel data. _ LED DISPLAYS _ The two display boards contain the LEDs that display alphanumeric information associated with each shaft encoder. The LEDs on the upper display board also display self-test status. 2-4 Functional Description 2.1.1 68000 Microprocessor The 68000 microprocessor (Figure 2-2) is used as a high-speed peripheral controller. It manipulates data from the shaft encoders, supplies data to the LED displays, handles interrupts, transfers status and data between the dial array and peripheral repeater, and executes commands from the peripheral repeater. In diagnostic mode, the 68000 runs the self-test diagnostics. (For more information on the 68000 microprocessor, see the manufacturer's literature.) Functional Description 2-5 Figure 2-2: 68000 Microprocessor Block Diagram ASD-1190 2-6 Functional Description Figure 2-3 is a map of dial array address space. Figure 2-3: Dial Array Address Space 2.1.2 ROM The two 8-kbyte ROMs (Figure 2-4) respond to addresses in the range 8000 through BFFF. Address bits are interpreted as follows: Functional Description 2-7 ____________________________________________________ Address Bits A15:A0 15 14 13:1 0 ____________________________________________________ 1 0 aaaaaaaaaaaaa b CEMRO L ROM address Byte Chip select UDS L = upper byte ____________________________________________________ LDS L = lower byte Signal CEMRO L from the chip enable logic # (Section 2.1.7) is equivalent to = 102. It is the chip select signal, and effectively selects ROM address space. Bits address one of the 8k locations in both ROMs. At power-up, the 68000 fetches its 32-bit SSP (Supervisor Stack Pointer) from memory locations 000000 and 000002, and its 32-bit PC (Program Counter) from memory locations 000004 and 000006. At this time, CEMRO L is effectively asserted by signal FORCE L from the power-up/reset logic (Section 2.1.8). This converts addresses in the range 000000 through 000006 to addresses in the range 008000 through 008006. AS L is asserted with every 68000 bus cycle, and increments the FORCE L shift-register count (Figure 2-11). After four bus cycles, FORCE L is deasserted. Subsequent ROM access is controlled by A15 and A14. Data strobe signals UDS L and LDS L from the 68000 enable output from the most significant (upper) or least significant (lower) byte ROM. These data strobe signals are equivalent to the two states of 68000 internal address bit A0. When UDS L is asserted, the upper ROM asserts . When LDS L is asserted, the lower ROM asserts . ________________ In the block diagrams, signals are asserted high # unless state indicator L is included after the signal name. 2-8 Functional Description The 68000 reads the ROMs during state seven of the read bus cycle. No wait states are inserted into the bus cycle and the entire bus cycle is completed in eight states (Section 2.1.9). 2.1.3 RAM The two 2-kbyte RAMs (Figure 2-4) respond to addresses in the range 0000 through 0FFF. Address bits are interpreted as follows: ____________________________________________________ Address Bits A15:A0 13:12 15 14 11:1 0 ____________________________________________________ 0 0 xx[1] aaaaaaaaaaa b Chip RAM address Byte select UDS L = CEMRAU L = CEMRA L Upper byte CEMRA L LDS L = CEMRAL L = Lower byte ____________________________________________________ [1]x = don't care ____________________________________________________ Signals CEMRAU L and CEMRAL L are the chip select signals, and are derived from CEMRA L, UDS L, and LDS L. Signal CEMRA L (Section 2.1.7) is equivalent to = 00, and is effectively a select signal for RAM address space. Address bits A13 and A12 are ignored, and select one of the 2k locations in both RAMs. Functional Description 2-9 Figure 2-4: Memory Block Diagram ASD-1198 2-10 Functional Description Data strobe signals UDS L and LDS L from the 68000 enable output from the most significant (upper) or least significant (lower) byte RAM. These data strobe signals are equivalent to the two states of 68000 internal address bit A0. When CEMRA L and UDS L are asserted, CEMRAU L is asserted and the upper RAM is enabled for read/write operations; when CEMRAU L and UDS L are asserted, CEMRAL L is asserted and the lower RAM is enabled for read/write operations. Signal R/W L from the 68000 is asserted for write operations and deasserted for read operations. The 68000 reads or writes the RAMs during state seven of the bus cycle. No wait states are inserted into the bus cycle and the entire bus cycle is completed in eight states (Section 2.1.9). 2.1.4 DUART The DUART (Figure 2-5) transmits (TTL) and receives (RS423) serial data between the dial array and the peripheral repeater. The DUART can also receive RS232 signals. Electrostatic discharge/electrical overstress (ESD/EOS) protection is provided for serial data input and output. Functional Description 2-11 Figure 2-5: DUART Block Diagram ASD-1191 2-12 Functional Description The DUART address range is E000 through EFFF; however, the only valid DUART addresses are in the range E000 through E01F. Address bits are interpreted as follows: ____________________________________________________ Address Bits A15:A0 15 14 13 12:5 4:1 0 ____________________________________________________ 1 1 1 xxxxxxxx[1]rrrr x Enable Register EN L address ____________________________________________________ [1]x = don't care ____________________________________________________ The DUART is enabled by signal EN L from the chip enable logic (Section 2.1.7). One condition for EN L is = 1112. Address bits are ignored. Address bits select one of the DUART internal registers (Table 2-1). ____________________________________________________ Table 2-1: DUART Internal Registers Address Read Write ____________________________________________________ A4 A3 A2 A1Register Register Channel A Functional Description 2-13 ____________________________________________________ Table 2-1 (Continued): DUART Internal Registers Address Read Write ____________________________________________________ A4 A3 A2 A1Register Register 0 0 0 0Mode 1 and 2 Mode 1 and 2 Status Clock Select 0 0 0 1(reserved) Command RX Holding TX Holding 0 0 1 0Input Port Auxiliary Control Change Interrupt Mask 0 0 1 1Interrupt C/T Upper Status C/T Lower 0 1 0 0Counter/Timer Upper 0 1 0 1Counter/Timer Lower 0 1 1 0 0 1 1 1 Channel B 1 0 0 0Mode 1 and 2 Mode 1 and 2 Status Clock Select 1 0 0 1(reserved) Command RX holding TX holding 1 0 1 0(reserved) (reserved) Input Port Output Port Control 1 0 1 1Start Counter Set Output Port Bits Command Command 1 1 0 0Stop Counter Reset Output Port Bits Command Command 1 1 0 1 1 1 1 0 1 1 1 1 ____________________________________________________ 2-14 Functional Description The DUART generates three interrupts to the 68000: RBINTR L, RAINTR L, and CINTR L. When the 68000 acknowledges the interrupts, EN L is disabled to prevent an erroneous response from the DUART. Read and write operations are enabled when RDN L (read) or UWR L (write) is asserted by the read/write logic (Section 2.1.10). The pulse width of UWR L is approximately 400 ms. The write occurs on a low-to-high signal transition during state six of the 68000 write cycle. DUART read and write operations cause four wait states to be added to the normal 8-state 68000 bus cycle (Section 2.1.9). The entire bus cycle is completed in 12 clock states. 2.1.5 Quadrature Decoders Figure 2-6 is a block diagram of the quadrature decoders. The 68000 reads the eight quadrature de- coders to get shaft encoder positional information. Decoder input is two pulse trains (CHANNEL A and CHANNEL B) from the associated shaft encoder. The number of pulses provides an incremental count and the phase relationship between the two trains indicates direction. The 12-bit decoder output is passed to the 68000 over in two successive read operations. Three signals control the read operation for each decoder: UDS L, OEn L, and RST-n L (where n is the decoder number). The 68000 upper data strobe, UDS L, selects the byte. When UDS L is asserted (low), the upper byte (4 bits) is read; when UDS L is deasserted (high), the lower byte (8 bits) is read. Output enable signals OE1 L through OE8 L come from a decoder in the chip enable logic (Section 2.1.7). This output enable decoder responds to addresses in the range C030 through C03E. Functional Description 2-15 After the 12 bits of decoder information have been transferred to the 68000, the decoder must be reset to zero to prevent a "hangup" in the decoder's internal inhibit logic. Quadrature decoder reset signals RST-1 L through RST-8 L come from a latch in the power-up/reset logic (Section 2.1.8). Quadrature encoder read cycles cause four wait states to be added to the normal 8-state 68000 bus cycle (Section 2.1.9). The entire bus cycle is completed in 12 clock states. 2-16 Functional Description Figure 2-6: Quadrature Decoders Block Diagram ASD-1192 Functional Description 2-17 2.1.6 Alphanumeric Displays (LEDs) The alphanumeric segmented-LED displays and their associated decoder logic are contained on two display boards. The upper display board contains LEDs for the top row of four shaft encoders, and the lower display board contains LEDs for the bottom row of four shaft encoders. The LED display for each shaft encoder consists of two 4- character display devices, for a total of eight characters per shaft encoder. The displays operate in alphanumeric mode. Cursor mode operations are not supported in the VSXXX-DA Dial Array. Figure 2-7 shows the eight LEDs for one shaft encoder. Each of the LEDs contains 16 segments and a radix point. Figure 2-7: Segmented-LED Displays ASD-1201 The display boards receive all required data, address, control signals, and power from the logic board. The board interface is shown in Figure 2-8. 2-18 Functional Description Figure 2-8: Logic Board/Display Board Interface Diagram ASD-1199 Functional Description 2-19 The display boards (Figure 2-9) respond to addresses in the range C000 through C00E (upper board) and C010 through C01E (lower board). Figure 2-9: Display Board Block Diagram ASD-1200 2-20 Functional Description These addresses are interpreted as follows: ____________________________________________________ Address Bits A15:A0 15 14 13 12:6 5 4 3:1 0 ____________________________________________________ 1 1 0 xxxxxxx[1]0 d sss x Enable Enable both CE1 decoder CE2 CE1 decoders select CE2 L A5 = 0 000 = CE1-1 Upper CE1 L decoder 001 = CE1-2 enable L A4 = 1 010 = CE1-3 Lower CE1 L decoder 011 = CE1-4 enable L A4 = 0 100 = CE1-5 L 101 = CE1-6 L 110 = CE1-7 111 = CE1-8 L ____________________________________________________ [1]x = don't care ____________________________________________________ Signal CE2 L is equivalent to = 1102 and AS. It is the CE2 enable for the displays. The CE1 enable for the displays comes from the CE1 decoder on the display boards. Each CE1 decoder has three enable signals. Address bit A4 = 0 is an enable for the CE1 decoder on the lower display board, and A4 = 1 is an enable for the CE1 decoder on the upper display board. Address bit A5 = 0 and R/W L (asserted low = write operation) are the other two enables for both CE1 decoders. Address bits select one of eight decoder outputs. Functional Description 2-21 The LED display devices store 7-bit ASCII charac- ters, loaded from . Characters are stored in one of four memory locations selected by . Data write is enabled when the cursor select signal CULD L is deasserted (high). Memory is written on a low-to-high transition of the 135 ns WR L signal from the read/write logic (Section 2.1.10). Stored ASCII characters are displayed when the cursor enable signal CUEAn is deasserted (low). The cursor enable signals come from the cursor enable latch. This latch is controlled by the cursor/data decoder. The cursor enable latch and cursor/data decoder respond to addresses in the range C000 through C016. These addresses are interpreted as follows: ____________________________________________________ Address Bits A15:A0 15 14 13 12:6 5 4:2 1:0 ____________________________________________________ 1 1 0 xxxxxxx[1]0 sss xx Decoder Decoder Latch select enable enable 000 = CUEA0 CE2 L A5 = 0 001 = CUEA1 010 = CUEA2 011 = CUEA3 100 = CUEA4 101 = CUEA5 110 = CUEA6 111 = CUEA7 ____________________________________________________ [1]x = don't care ____________________________________________________ Cursor/data decoder operation depends on three enable signals. One enable signal is CE2 L, which is equivalent to = 1102 and AS. Address bit A5 = 0 is another enable for the decoder. The final decoder enable is FUN EN L from the wait state generator (Section 2.1.9). Wait state signal Q0 is ANDed with Q3 L to assert FUN EN L for approximately 400 ms. 2-22 Functional Description Only three of the cursor/data decoder outputs are implemented. They are selected by as follows: ____________________________________________________ DATA ____________________________________________________ 11 10 9 Output 0 1 1 CUR/DAT L Enables the cursor enable latch. 0 1 0 DISPLAY DATA ALL L Resets the cursor enable latch. This deasserts the latch outputs (low) allowing stored ASCII characters to be displayed. 0 0 0 CU LD L Enables the cursor to be loaded in the display device. CU LD L should always be deasserted (high) when the displays are being ____________________________________________________ written. Cursor enable latch outputs are used on the upper display board, and are used on the lower display board. The outputs are selected by as described above. The latch is enabled by CUR/DAT L from the cursor/data decoder, and reset by DISPLAY DATA ALL L from the cursor/data decoder. The selected output is asserted (high) when DATA 13 = 1, and deasserted (low) when DATA 13 = 0. To display the ASCII characters in one 8-character set of displays, the selected output is deasserted. Functional Description 2-23 2.1.7 Chip Enable Logic The majority of the signals which enable the various devices are developed in the chip enable logic (Figure 2-10). Figure 2-10: Chip Enable Logic Block Diagram ASD-1194 2-24 Functional Description Signal CEMRO L is equivalent to = 102 and is the ROM chip select signal . At power-up, # CEMRO L is effectively asserted by signal FORCE L from the power-up/reset logic (Section 2.1.8). This is done to convert the 68000 32-bit SSP and PC virtual addresses from 000000 and 000004 to physical addresses 008000 and 008004 in ROM. AS L is asserted with every 68000 bus cycle, and increments the FORCE L shift-register count (Figure 2-11). After four bus cycles, FORCE L is deasserted. Subsequent ROM access is controlled by A15 and A14. Signal CEMRA L is equivalent to = 00, and is effectively a select signal for RAM address space. Signal EN L enables the DUART and is derived from CEN L and 68000 signals : _ Signal CEN L is asserted when = 1112 _ and AS is asserted; AS is asserted (high) at the same time when AS L is asserted (low). _ The 68000 asserts when it acknowledges _ DUART interrupts. These lines are ANDed with AS to produce VPA L, which disables EN L to prevent the DUART from responding to an invalid CEN L signal. Deasserting any of the signals enables EN L. _ Asserting VPA L on an interrupt acknowledge _ cycle causes the 68000 to perform an internal vector generation operation. An external bus cycle occurs, but no valid information is taken from the bus. Signals OE1 L through OE8 L from a 1-of-8 decoder enable quadrature decoder output. This output enable decoder responds to addresses in the range C030 through C03E. ________________ In the block diagrams, COM LOG indicates combina- # tional logic. Functional Description 2-25 These addresses are interpreted as follows: ____________________________________________________ Address Bits A15:A0 15 14 13 12:6 5 4 3:1 0 ____________________________________________________ 1 1 0 xxxxxxx[1]1 1 sss x Enable Enable Select CE2 L 000 = OE1 L 001 = OE2 L 010 = OE3 L 011 = OE4 L 100 = OE5 L 101 = OE6 L 110 = OE7 L 111 = OE8 L ____________________________________________________ [1]x = don't care ____________________________________________________ Signal CE2 L is equivalent to = 1102 and AS. It is ANDed with A5 to assert CE2 A5 L. Signals CE2 A5 L and A4 are the enable for the output enable decoder. Address bits select one of the eight decoder outputs. Address bits and A0 are ignored. 2.1.8 Power-Up/Reset Logic The power-up/reset logic (Figure 2-11) provides resets to the 68000, DUART, display boards, and quadrature decoders. It also generates FORCE L for the chip enable logic, to enable ROM at power-up. Approximately 55 ms after power-up, the input is disabled, but the time-constant of the 1-shot keeps the outputs active for approximately 300 ms. The reset outputs are fanned-out to other devices through an 8-bit latch and combinational logic. The 1-shot can also be triggered by a low-to-high transition on pin J12-1 (signal SMART). This input is used to initiate manufacturing mode self-test. 2-26 Functional Description The logic for signal 68RES L comprises a two-input NOR gate and an inverter. One NOR gate input is RESET L and the other is +5V. By pulling the +5V input low, Automated Test Equipment (ATE) can assert 68RES L to reset the 68000 microprocessor indepent of the power-up logic. Figure 2-11: Power-Up/Reset Logic Block Diagram ASD-1193 Signals RESA L and RESB L reset the two display boards. The displays reset pulse width must no be less than 4 ms. Signals RST-1 L through RST-8 L from an 8-bit latch reset the quadrature decoders. The latch responds to addresses in the range C020 through C02E to set the latch and C060 through C06E to reset the latch. These addresses are interpreted as follows: Functional Description 2-27 ____________________________________________________ Address Bits A15:A0 15 14 13 12:7 6 5 4 3:1 0 ____________________________________________________ 1 1 0 xxxxxx[1] r 1 0 sss x Enable Set latch Select CE2 L A6 = 0 000 = RST-1 Reset latch L A6 = 1 001 = RST-2 Enable latch L A5 = 1 010 = RST-3 Disable OE L decoder 011 = RST-4 A4 = 0 L 100 = RST-5 L 101 = RST-6 L 110 = RST-7 111 = RST-8 L ____________________________________________________ [1]x = don't care ____________________________________________________ Signal CE2 L is equivalent to = 1102 and AS. It is ANDed with A5 to assert CE2 A5 L, the enable for the reset latch. When A6 = 0, the selected latch is set, deasserting the corresponding RST-n L output (high). When A6 = 1, the selected latch is reset, asserting the corresponding RST-n L output (low) to reset the corresponding quadrature decoder. Address bit A4 is 0, disabling the output enable decoder in the chip enable logic (Section 2.1.7). Address bits select one of the eight latches. Address bits and A0 are ignored. 2-28 Functional Description 2.1.9 Wait State Generator The wait state generator (Figure 2-12) generates DTACK L to control 68000 bus cycles, timing signals Q3 L and Q0 to control DUART write pulse width, Q1 and Q2 L to control memory write timing for the LED display devices, and FUN EN L to control cursor/data decoder timing for the LED display devices. The 68000 reads the ROMs during state seven of the read bus cycle. In response to ROM read cycles, wait state logic returns DTACK L to the 68000 when CEMRO L is asserted. Because this occurs prior to state four of the 68000 bus cycle, no wait states are inserted into the bus cycle and the entire bus cycle is completed in eight states. Similarly, the 68000 reads or writes the RAMs during state seven of the bus cycle. In response to RAM read or write cycles, wait state logic returns DTACK L to the 68000 when CEMRA L is asserted. Because this occurs prior to state four of the 68000 bus cycle, no wait states are inserted into the bus cycle and the entire bus cycle is completed in eight states. Unlike ROM and RAM accesses, DUART read/write operations and quadrature decoder read operations cause four wait states to be added to the normal 8- state 68000 bus cycle. The wait state generator is enabled (CLR input deasserted) when CE is asserted. CE is asserted when = 112 and AS is asserted. After the wait state generator is asserted, the rising edge of the third 7.3728 MHZ L clock signal causes DTACK L to be asserted. When the 68000 senses DTACK L, it completes the cycle in progress. The entire bus cycle is completed in 12 clock states. Functional Description 2-29 Figure 2-12: Wait State Generator Logic Block Diagram ASD-1196 2-30 Functional Description 2.1.10 Read/Write Logic The read/write logic (Figure 2-13) generates read/write signals for the DUART and write signals for the LED display devices. Signal RDN L enables DUART read operations. It is derived from EN L and 68000 signal R/W L. When EN L is asserted and R/W L is deasserted (high), RDN L is asserted. Signal UWR L enables DUART write operations. It is derived from EN L, 68000 signal R/W L, and wait state generator signals Q3 L and Q0. When EN L and R/W L are asserted, a DUART write operation is enabled. These signals are then ANDed with Q3 L and Q0 to give UWR L a pulse width of approximately 400 ms. Signal WR L enables write operations to LED display device memory. It is derived by ANDing Q1 and Q2 L from the wait state generator with LDS; LDS is asserted (high) at the same time as LDS L (low). The pulse width of WR L is approximately 135 ns. Functional Description 2-31 Figure 2-13: Read/Write Logic Block Diagram ASD-1195 2.1.11 Clocks The 7.3728 MHz and 3.6864 MHz system master clocks are provided by a dual-frequency crystal oscillator (Figure 2-14). The 7.3728 MHZ L signal is the clock for the 68000 microprocessor and the wait state logic. The 3.6864 MHz and 3.6864 MHz L signals are the DUART clocks. Signal HCTCLK is also 3.6864 MHz, for quadrature decoder timing. The clock outputs have tristate capability for ATE coverage. 2-32 Functional Description Figure 2-14: Clock Block Diagram ASD-1197 2.2 Operational Firmware The dial array operational and diagnostic firmware is contained in 16 kbytes of ROM. The diagnostic firmware, including self-test, is described in Chapter 3. The 68000 microprocessor executes all firmware. 2.2.1 Power-up The dial array receives its power from the peripheral repeater. When power is applied, the power-up self-test diagnostic is run. Depending on the state of signal SMART (Section 2.1.8), self- test runs in either manufacturing mode or user mode (also called customer mode) with the following possible results: _ Manufacturing mode _ Functional Description 2-33 In this mode, self-test is run continuously, and the dial array does not go into operational mode. If an error is detected, self-test loops on the failing test and the failing test number is displayed in the LED displays. _ User mode _ If an error is detected, self-test halts and question marks (?) are displayed in all LED displays. The dial array cannot communicate with the peripheral repeater. If no errors are detected, asterisks (*) are displayed in all LED displays, the dial array enters operational mode and can communicate with the peripheral repeater. 2.2.2 Operational Mode In operational mode, the operational firmware is executing. The dial array executes commands received from the host through the peripheral repeater, manipulates shaft encoder data, and drives the LED displays. The microprocessor processes interrupts and transfers status and data to the host through the peripheral repeater. ____ Note ___ __________ ________ ____ ___ ________ ________ The peripheral repeater does not initiate commands __ _________ __________ __ __ ____ _ ____________ or interpret responses; it is only a concentrator _______ ___ ____ ___ ___ ________ ___________ between the host and the graphics subsystem's ___________ ________ _____ _______ ___ ____ ______ interactive devices, which include the dial array. ___ ____ __ ____ _______ __ _ ________ _______ The host in this context is a graphics control __________ ____ __ ___ _____ __ ___ __________ processor, such as the KA825 in the VAXstation _____ 8000. The operational firmware executes in one of three modes: _ Local loopback mode _ _ Message mode _ _ LED Segment mode _ 2-34 Functional Description 2.2.2.1 Local Loopback Mode The dial array enters local loopback mode immedi- ately after the successful completion of power-up self-test. This mode allows each of the eight en- coder/LED sets to be separately tested. When this mode is entered, all the LED displays are initially set to zero. The encoders are tested by slowly turning each knob and observing the count in the associated LED display. Turning the knob clockwise increases the count; turning it counterclockwise decreases the count. The maximum count is 4095. The shaft encoders have no stops and can be continuously rotated in either direction. Clockwise rotation be- yond 4095 restarts the count at 0; counterclockwise rotation beyond 0 restarts the count at 4095. The dial array remains in local loopback mode until it receives a character other than CTRL/E from the host. (Commands, control characters, messages, and reports are described in Section 2.2.3.) The dial array reenters local loopback mode when it receives a CTRL/D character from the host. 2.2.2.2 Message Mode In this mode, the dial array transmits encoder rotation information to the host. When any encoder knob is turned, the encoder generates output pulses, called Rotational _______ deltas. information is in terms of relative delta values; that is, the position of any encoder's shaft is reported in terms of the direction and the amount of change relative to its previously sampled position. After power is applied, but before any rotational information is transmitted to the host, two dial array operating parameters must be set with commands from the host: Functional Description 2-35 1. The minimum rotation-count delta required before a sample is transmitted to the host. This parameter is set with a Rotation Count Delta command (Section 2.2.3.6). 2. The maximum rate at which the dial array transmits delta updates to the host. This parameter is set with the Maximum Update Count command (Section 2.2.3.7). Dial array logic uses the encoder output pulses, or deltas, to determine the following: _ Which encoder's shaft is rotating _ _ The direction of rotation _ _ The amount of rotation; encoder shaft position _ is evaluated in terms of deltas. After the rotational information is processed by the dial array logic, it is transmitted to the host as an Update Count message (see Section 2.2.3.8). 2.2.2.3 LED Segment Mode Each of the eight 8-character LED displays is a label, or readout, for its associated shaft encoder. The LED displays are always operated in LED Segment Mode. In this mode, each display is separately programmed and operates independently of the other LED displays. The LED displays are programmed with a LED Label Message command (Section 2.2.3.9). 2-36 Functional Description 2.2.3 Commands, Messages, and Reports This section describes the commands, messages, and reports transferred between the dial array and the host. ____ Note ___ _________ ________ ___ ________ _________ __ The commands, reports, and messages described in ____ _______ ___ ___________ ____ ______ ______ this section are transmitted over serial lines, _____ ___________ ____ ______ ___ ________ __ ___ least significant byte first. For example, in the ________ __ _ ______ ________ ________ ____ _ __ response to a Report Revision command, byte 0 is ___________ ______ ____ _ __ ___________ _____ transmitted first, byte 5 is transmitted last. ________ ___ _______ ___ _____ __ ___ ________ However, all formats are shown in the "normal" ______ ____ ___ ____ ___________ _____ ___ _____ __ order, that is, most significant bytes are shown on ___ ____ ___ _____ ___________ _____ ___ _____ __ the left and least significant bytes are shown on ___ ______ the right. 2.2.3.4 Local Loopback Command The host transmits this 1-byte command to the dial array to put the dial array into Local Loopback Mode. The command is an ASCII CTRL/D (416). There is no response to this command. 2.2.3.5 Revision Report Command The host transmits this 1-byte command to the dial array and receives a 6-byte response. The command is an ASCII CTRL/E (516). The response is described in Section 2.2.3.3. 2.2.3.3 Revision Report The dial array transmits this report in response to a Revision Report command from the host. The report format is shown in Figure 2-15 and described in Table 2-2. Functional Description 2-37 Figure 2-15: Revision Report Format ASD-1202 ____________________________________________________ Table 2-2: Revision Report Description ____________________________________________________ Byte Name Description 5:4 CD ASCII characters CD (4316 and 4416), identifying the reporting device as the dial array. 3:1 ROM Three-digit hexadecimal ROM revision REVISION level. LEVEL 0 LEDS A single ASCII character that indicates if the dial array includes segmented-LED displays: D (6416) = Displays are present. N (6E16) = Displays are not present. For the VSXXX-DA, this byte always equals D. ____________________________________________________ 2.2.3.4 Self-Test Command The host transmits this 1-byte command to the dial array to cause the dial array to execute self-test. In response to this command, the dial array executes self-test and transmits a Self-Test Report. The command is an ASCII CTRL/S (1316). The response is described in Section 2.2.3.5. 2-38 Functional Description 2.2.3.5 Self-Test Report The dial array transmits this report after executing self-test. The report format is shown in Figure 2-16 and described in Table 2-3. Figure 2-16: Self-Test Report Format ASD-1203 ____________________________________________________ Table 2-3: Self-Test Report Description ____________________________________________________ Byte Name Description 1 STATUS A 2-digit hexadecimal value that indicates the results of self-test. See Figure 2-17 and Table 2-4. 0 CTRL/R An ASCII CTRL/R (1216) character that indicates that the dial array is responding and the next byte contains status information. ____________________________________________________ Functional Description 2-39 Figure 2-17: Self-Test Command Status Byte Format ASD-1204 ____________________________________________________ Table 2-4: Self-Test Status Byte Description Hexadecimal ____________________________________________________ Value Description 00 Self-test executed with no errors. 11 ROM test failed (there are no ROM subtests). 22 RAM test failed (there are no RAM subtests). 13 UART test failed register subtest. 23 UART test failed polling subtest. 33 UART test failed internal interrupt subtest. 43 UART test failed counter subtest. 53 UART test failed external interrupt subtest. ____________________________________________________ 2.2.3.6 Rotation Count Delta Command This 4-byte command specifies the minimum number of deltas that must be output from a given encoder before an updated rotation count is transmitted to the host. The command format is shown in Figure 2-18 and described in Table 2-5. 2-40 Functional Description Figure 2-18: Rotation Count Delta Command Format ASD-1205 ____________________________________________________ Table 2-5: Rotation Count Delta Command Description ____________________________________________________ Byte Name Description 3 LSBYTE The least significant byte and most MSBYTE significant byte specify the 15- 2 bit delta value. The value can be between 1 and 7FFF16. Zero and negative values are not recommended. [1] 1 CTRLBYTE The control byte specifies the shaft encoder number in the format shown in Figure 2-19 and described in Table 2-6. 0 CTRL/V An ASCII CTRL/V (1616) character. ____________________________________________________ [1]To interpret this value, LSBYTE and MSBYTE must be swapped. For example, the value 0A7F is transmitted as 7F0A. ____________________________________________________ Functional Description 2-41 Figure 2-19: Rotation Count Delta Command Control Byte Format ASD-1206 Table 2-6: Rotation Count Delta Command Control ____________________________________________________ Byte Description ____________________________________________________ Bits Name Description 07:03 A unique identifier for the Rotation Count Delta command control byte. Bit <07> must be 1, bit <05> must be 0, and bits <06,04:03> can be 0 or 1. 02:00ENCODER The binary-coded encoder number, from 0 through 7. ____________________________________________________ 2.2.3.7 Maximum Update Count Command This 4-byte command specifies the maximum rate, in seconds, at which the new delta count for any shaft encoder can be transmitted to the host. The dial array then transmits Update Count messages at this rate. The command format is shown in Figure 2-20 and described in Table 2-7. The Update Count message is described in Section 2.2.3.8. 2-42 Functional Description Figure 2-20: Maximum Update Count Command Format ASD-1207 ____________________________________________________ Table 2-7: Maximum Update Count Command Description ____________________________________________________ Byte Name Description 3 RATE The maximum number of updates per second, specified as a hexadecimal value: 60 updates/s = 0516 30 updates/s = 0A16 10 updates/s = 1E16 2 RESERVED Reserved, not used. 1 CTRLBYTE This is a unique identifier for the Maximum Update Count command control byte. It has the format shown in Figure 2-21 and described in Table 2-8. 0 CTRL/V An ASCII CTRL/V (1616) character. ____________________________________________________ Functional Description 2-43 Figure 2-21: Maximum Update Count Command Control Byte Format ASD-1208 Table 2-8: Maximum Update Count Command Control ____________________________________________________ Byte Description ____________________________________________________ Bits Name Description 07:00 Bits <07,05> must be 1 and bits <06,04:00> can be 0 or 1. ____________________________________________________ 2.2.3.8 Update Count Message This message is transmitted by the dial array at the rate determined by the Maximum Update Count command. The message format is shown in Figure 2-22 and described in Table 2-9. Figure 2-22: Update Count Message Format ASD-1209 2-44 Functional Description ____________________________________________________ Table 2-9: Update Count Message Description ____________________________________________________ Byte Name Description 3 LSBYTE The least significant byte and most significant byte contain the signed 2 MSBYTE 15-bit delta value. A negative value indicates counterclockwise rotation of the encoder shaft, and a positive value indicates clockwise rotation. The value can be between the minimum value specified by the Rotation Count Delta command and 7FFF16. [1] 1 ENCODER The number of the encoder generating the count. 0 CTRL/V An ASCII CTRL/V (1616) character. ____________________________________________________ [1]To interpret this value, LSBYTE and MSBYTE must be swapped. For example, the value 0A7F is transmitted as 7F0A. ____________________________________________________ 2.2.3.9 LED Label Message Command This 10-byte command determines what characters are displayed in the LED display associated with a given encoder. The command format is shown in Figure 2-23 and described in Table 2-10. Functional Description 2-45 Figure 2-23: LED Label Message Command Format ASD-1210 ____________________________________________________ Table 2-10: LED Label Message Command Description ____________________________________________________ Byte Name Description 9:2 CHAR 8:1 The ASCII codes for the eight characters to be displayed in the segmented-LEDs associated with the encoder specified in byte 1. Blank characters (ASCII space, 2016) must also be specified. The characters can be any ASCII character in the range of ASCII codes from 2016 through 5F16. 1 CTRLBYTE The control byte specifies the number of the shaft encoder associated with the message coded in bytes <9:2>. The control byte format is shown in Figure 2-24 and described in Table 2-11. 0 CTRL/V An ASCII CTRL/V (1616) character. ____________________________________________________ 2-46 Functional Description Figure 2-24: LED Label Message Command Control Byte Format ASD-1211 Table 2-11: LED Label Message Command Control Byte ____________________________________________________ Description ____________________________________________________ Bits Name Description 07:03 A unique identifier for the LED Label Message command control byte. Bits <07,03> must be 0; bits <06:04> can be 0 or 1. 02:00ENCODER The binary-coded encoder number (0 through 7). ____________________________________________________ Functional Description 2-47 Chapter 3 Diagnostics _______________________________________________________ The dial array operational and diagnostic firmware are contained in the 16-kbytes of ROM. The dial array operates in either operational mode, when it is executing operational firmware, or in diagnostic mode, when it is executing self-test. The 68000 microprocessor executes all the firmware. Operational mode and operational firmware are described in Chapter 2. This chapter describes the dial array diagnostics. 3.1 Self-test Self-test is the only dial array diagnostic. It is run when power is applied to the dial array (from the peripheral repeater). It runs in either user mode (also called customer mode) or manufacturing mode. Diagnostics 3-1 3.1.1 User Mode In user mode, self-test is executed at power-up or when requested by peripheral repeater command (see Section 2.2.3.4). If an error is detected in user mode, self-test halts, and question marks (?) appear in all LED displays. The dial array cannot communicate with the peripheral repeater. To run the tests again, power must be removed and reapplied to the dial array; that is, the peripheral repeater must be turned off and then on. If no errors are detected, asterisks (*) are displayed in all LED displays, the dial array enters operational mode, and can communicate with the peripheral repeater. 3.1.2 Manufacturing Mode In manufacturing mode self-test executes contin- uously and the dial array does not go into oper- ational mode. If an error is detected in manufac- turing mode, self-test loops on the failing test, and the failing test number is displayed in the LED displays. The dial array is placed in manufacturing-mode self-test with a special loopback connector. The power-up/reset 1-shot (Figure 2-11) can be triggered by a low-to-high transition on pin J12- 1 (signal SMART). This input is used to initiate manufacturing-mode self-test. The logic for signal 68RES L comprises a two-input NOR gate and an inverter. One NOR gate input is RESET L and the other is +5V. By pulling the +5V input low, Automated Test Equipment (ATE) can assert 68RES L to reset the 68000 microprocessor indepent of the power-up logic. 3-2 Diagnostics For manufacturing burn-in, DUART signal EOP H (Figure 2-5) is output on J12 pin 2 to the smart burn-in host. A hardware reset deasserts EOP H (low). The EOP (end-of-pass) signal goes from a low-to-high state at the end of every successful self-test pass. It remains high for approximately 400 us and then goes low. If a failure occurs, EOP remains low. A voltage divider network at the 9639 EIA receiver input to the DUART detects a logic level transition of approximately +1.5 V. This special transition level is for manufacturing-mode loopback self-test operations. 3.2 Diagnostic Description Self-test tests ROM, RAM, and the DUART, and reports status to the peripheral repeater (see Section 2.2.3.5). The self-test subtests are described in the following sections. 3.2.1 ROM Test A check sum is calculated and compared to a stored value. If an error is detected, the dial array reports a ROM test failure to the peripheral repeater (see Section 2.2.3.5). 3.2.2 RAM Data/Address Test This test detects addressing errors as well as read/write errors. It is a modified march pattern, performed in three passes. The first pass is write only. The second pass reads, compares, complements, and writes the entire available memory. It starts at the lowest available address and ends at the highest memory address. The third pass is the reverse of the second pass, that is, it starts at the highest address, and ends at the lowest available address. If an error is detected, the dial array reports a RAM test failure to the peripheral repeater (see Section 2.2.3.5). Diagnostics 3-3 3.2.3 DUART Tests DUART register read/write tests verify various accessible registers including DUART Mode Registers 1 and 2, and Command, Status, Receive Data, and Transmit Data registers. The mode registers are verified by writing patterns to the registers and reading them back. Different patterns are written to the two registers on each pass, to check for unique addressing. The Command, Status, Receive Data, and Transmit Data registers are verified by using the DUART internal diagnostic loopback capabilities. The DUART interrupt test checks the DUART receive interrupt logic. If an error is detected, the dial array re- ports a DUART test failure to the peripheral re- peater. One of five errors can be reported (see Section 2.2.3.5). 3.2.4 LED Tests Before ROM, RAM, and the DUART are tested, self-test determines if the dial array is in manufacturing mode. Then, after ROM, RAM, and the DUART pass, various patterns are displayed in the LEDs. In manufacturing mode, the LEDs display the following ASCII characters and their complements: Character P 5 U Complement / J * These characters provide the best exercise for the LED addressing lines. 3-4 Diagnostics In user mode, asterisks (*) are displayed on all LEDs, and then the dial array enters local loopback mode. Diagnostics 3-5 Chapter 4 Repair _______________________________________________________ The dial array is not usually repaired in the field; the entire unit is replaced. Dial array failures are indicated in two ways: by the dial LEDs and/or by ROM-based diagnostics (RBDs) for the KA800 (the KA800 is the graphics control processor in the VAXstation 8000). The dial array reports self-test status to the VSXXX-CA/CB Peripheral Repeater, and the peripheral repeater reports status to the KA800. Other than replacing the complete unit, the data cable between the dial array and peripheral repeater can be replaced. Table 4-1 lists the order numbers. ____________________________________________________ Table 4-1: Field Replaceable Units ____________________________________________________ Part Description Part Number Dial Array VSXXX-DA Data Cable, 1.32 m (52 in) 17-01416-01 ____________________________________________________ Repair 4-1 Index _______________________________________________________ __________________________ A Commands (cont'd.) Alphanumeric displays rotation count delta 2-18 2-40 ATE 2-27, 3-2 control byte description 2-42 __________________________ C control byte format Chip enable logic 2-24 2-41 block diagram 2-24 description 2-41 Clocks 2-32 format 2-40 block diagram 2-32 self-test 2-38 COM LOG 2-26 status byte format Commands 2-37 2-39 LED label message 2-45 CTRL/D 2-37 control byte CTRL/E 2-37 description 2-47 CTRL/R 2-39 control byte format CTRL/S 2-38 2-46 CTRL/V 2-40, 2-42, description 2-46 2-44, 2-45 format 2-45 __________________________ D local loopback 2-37 maximum update count Data cable part number 2-42 4-1 control byte Deltas 2-35 description 2-44 Diagnostics control byte format description 3-3 2-43 DUART tests 3-4 description 2-43 KA800 ROM-based 4-1 format 2-42 LED tests 3-4 revision report 2-37 manufacturing mode 3-2 _______ Index-1 __________________________ I Diagnostics (cont'd.) Interrupts 2-15 RAM data/address test 3-3 __________________________ K ROM test 3-3 KA800 4-1 self-test 3-1 Knobs box 1-1 user mode 3-2 Dial array __________________________ L address space 2-7 block diagram 2-2 LED Dial box 1-1 diagnostics 3-4 Display board/logic board label message command interface diagram 2-45 2-19 control byte Display board block description 2-47 diagram 2-20 control byte format DUART 2-11 2-46 block diagram 2-11 description 2-46 diagnostics 3-4 format 2-45 interrupts 2-15 segment mode 2-36 registers 2-13 Local loopback command 2-37 __________________________ E mode 2-35 Logic board/display board Electrical specifications interface diagram 1-2 Encoder/LED set 1-1 2-19 Environmental specifica- __________________________ M tions 1-3 Manufacturing mode 2-33, __________________________ F 3-2 Field replaceable units Maximum update count 4-1 command 2-42 Firmware control byte description operational 2-33 2-44 FRU control byte format data cable 4-1 2-43 dial array 4-1 description 2-43 format 2-42 __________________________ H Memory Hardware description 2-1 block diagram 2-9 Host 2-34 Message mode 2-35 _______ Index-2 Messages 2-37 Registers update count 2-44 DUART 2-13 description 2-45 Reports 2-37 format 2-44 revision report 2-37 68000 microprocessor 2-5 description 2-38 block diagram 2-5 format 2-37 Microprocessor 2-5 self-test 2-39 Mode description 2-39 LED segment 2-36 format 2-39 local loopback 2-35 Reset logic 2-26 manufacturing 2-33, 3-2 block diagram 2-27 message 2-35 Revision report 2-37 operational 2-34 command 2-37 user 2-34, 3-2 description 2-38 format 2-37 __________________________ ROM 2-7 diagnostics 3-3 Operational ROM-based diagnostics firmware 2-33 4-1 mode 2-34 Rotation count delta __________________________ P command 2-40 control byte description Part number 2-42 data cable 4-1 control byte format dial array 4-1 Physical specifications 2-41 description 2-41 1-2 format 2-40 Power-up 2-33 Power-up/reset logic __________________________ S 2-26 block diagram 2-27 Segmented-LED displays 2-18 __________________________ Q Self-test 3-1 command 2-38 Quadrature decoders 2-15 status byte format block diagram 2-16 2-39 __________________________ R report 2-39 description 2-39 RAM 2-9 format 2-39 diagnostics 3-3 status byte description RBD 4-1 2-40 Read/write logic 2-31 Specifications block diagram 2-31 _______ Index-3 format 2-44 Specifications (cont'd.) User mode 2-34, 3-2 electrical 1-2 environmental 1-3 __________________________ W physical 1-2 Wait state generator __________________________ U block diagram 2-29 Update count message Write/read logic 2-31 2-44 block diagram 2-31 description 2-45 _______ Index-4