<<< EISNER::$2$DIA6:[NOTES$READONLY]MICRONOTE.NOTE;1 >>> -< TOEM MicroNotes >- ================================================================================ Note 12.0 DMA on the Q-bus No replies JAWS::KAISER 174 lines 25-MAR-1985 09:20 -------------------------------------------------------------------------------- +---------------+ +-----------------+ | d i g i t a l | | uNOTE # 012 | +---------------+ +-----------------+ +----------------------------------------------------+-----------------+ | Title: DMA on The Q-bus | Date: 06-SEP-84 | +----------------------------------------------------+-----------------+ | Originator: Jack Toto | Page 1 of 4 | +----------------------------------------------------+-----------------+ This Micronote explains the various types of DMA on the Q-bus; Single Cycle Mode, Burst Mode and Block Mode. SINGLE CYCLE MODE: ------------------ Single cycle mode DMA like all DMA on the Q-bus requires that the DMA device gain control of the bus through an arbitration cycle. During the arbitration cycle the DMA device becomes bus master by first asserting a DMA request (BDMR). When the arbiter acknowledges this request it issues a DMA grant (BDMGO). In the event that there is more than one DMA device in the backplane the grant signal is daisy chained from device to device. Eventually the device that issued the DMA request will latch the grant signal and take control of the bus, and proceed with the DMA transfer. Once becoming bus master the device asserts BSACK and is allowed to do one word tranfer to or from memory, during which time the CPU is idle. Certain processors such as the KDJ11-B have a cache memory with dual tag store which allows it to process data while DMA transfers are occurring. Regardless of which processor type is used only one transfer is allowed in single cycle mode. If the device must perform additional transfers, it must go through the bus arbitration cycle again. _______________ _______________ SACK ___________/ \____________/ \_____ BDAL __________/ ADRS/DATA \___________/ ADRS/DATA \_____ 1 2 In single cycle mode, the theoretical transfer rate across the Q-bus is 1.66 Mbytes/sec (833Kw/sec) A device such as the DRV11-B or the newer 22-bit compatible DRV11-W can transfer data at a rate of 250KW/sec while in single cycle mode. Page 2 BURST MODE: ----------- Burst mode DMA can be performed by certain devices such as the DRV11-B. Once the DMA controller becomes bus master (through the arbitration routine described in the single cycle section and it has asserted BSACK, the DMA tranfers can begin. Each data word that is transfered is accompanied by an address that the data word is targeted for. In burst mode loading an octal value into the 16 bit word count register (WCR) allows for that number of words (64Kb max) to be transfered under one sack. This differs from single mode, in that the word count register can be loaded with the same value, but each single word transfer will require a new arbitraion cycle, i.e in order to transfer 64Kb of data it would require 65,536 arbitration cycles. ________________________________________________ SACK ____/ \____ BDAL ____/ADRS/DATA ADRS/DATA ADRS/DATA................(N)\____ N := word count; The theoretical transfer rate across the Q-bus in burst mode remains at 1.66 Mbytes/sec, however a device such as the DRV11-B operating in burst mode can transfer data at a rate twice that of a DRV11-B operating in single mode, or 500Kw/sec. In burst mode the DMA bus master maintains control of the bus until it has transferred all of the required data. Burst mode has the advantage of moving large blocks of memory across the bus with no delay. The caution here is that no other device (including the CPU) has access to the bus during that time. This can have severe impact on system performance. DMA COMPROMISE: -------------- Since Single Cycle Mode requires a rearbitration for every data transfer and Burst Mode can adverseley impact system performance in some cases DIGITAL EQUIPMENT CORP. has made some compromises with certain DMA controllers. Most DIGITAL devices will do a limited Burst Mode operation. These controllers (for example the RXV21 and RLV12) are allowed up to do four words of data tranfer. Each word of transfer is preceeded on the bus by an address that the data word is targeted for. This allows data to move across the bus with a minimum of rearbitraton. However, when a group of four transfers is finished, the DMA devices must again go through the arbitration cycle in order to allow other Page 3 devices the opportunity to use the bus. If no other bus requests are pending at a higher priority, then bus mastership will be returned to the device for the next set of data transfers. ______________________________________ SACK ___________/ \_______ BDAL ___________/ADRS/DATA ADRS/DATA ARDS/DATA ADRS/DATA\_______ 1 2 3 4 BLOCK MODE: ---------- For increased throughput, Block Mode DMA may be implemented on a device for use with memories that support this type of transfer. Block Mode DMA devices are only block mode when operating. They may not operate as a Single or Burst Mode device. They may, however, appear to operate like a single mode device if they are only doing a single word transfer, and they will always look like a Single Cycle Mode DMA device when used with non-Block Mode memory. Once a Block Mode device has arbitrated for the bus, the starting memory address is asserted, then data for that address, followed by data for consecuetive addresses. By eliminating the assertion of the address for each data word, the transfer rate is almost doubled. The DMA device should monitor the BDMR line. If the line is not asserted after the seventh transfer than the device can continue. This allows a maximum of 16 data transfers for one abitration cylce. If the BDMR line is not monitored by the DMA device than a maximum data tranfer of 8 words is allowed after completing one bus arbitration cycle. Block Mode DMA transactions can be described as two types, a DATBI (block mode data in) and DATBO (block mode data out). Both of these cycles are explained in depth in the Micronote's. When reading the appropriate micronote special attention should be paid to the use of BREF and BBS7 signals when performing a DATBO. ___________________________________________ SACK___/ \___ BDAL___/ADRS/DATA/.........DEPENDS ON STATE OF BDMR\___ (1) * (7) (16) | ___ | BDMR \____________________*_______________________/\/\/ Block Mode devices such as the DEQNA, RQDX1 and the MSV11-P memories can Page 4 transfer data across the bus at rates that approach twice that of DMA devices in Burst Mode. The actual rate is dependent upon the device itself. The technical manuals for each of these devices should be checked for actual performance figures.